Power delivery to base of processor

#This application claims priority of U.S. Provisional Patent Application Serial No. 60/359,548, filed Feb. 25, 2002.

#The present invention relates generally to delivering power to computer processors, and more particularly to apparatus and methods for delivering power to micro and other processors to the base, and preferably the center of the processor.

#The computer industry has seen a remarkable advancement over the years. Every few years, semiconductor companies are developing faster and more powerful chips, or processors, for use in desktop and notebook computers, as well as work stations. These more powerful processors have to operate at reduced voltages and higher currents. The need for supplying power to these processors presents design problems, especially in view of the high power requirements for processors, which may run as high as from about 200 amps to about 700 amps. One solution is to provide power supplies and/or conductive paths on the base or motherboard to which the processor is mounted. This is undesirable because the higher processor currents require the incorporation of large and thick copper traces in order to minimize voltage drop. This increases the cost of the motherboard. The traces must also be designed so as to provide very low loop inductance in order to stabilize voltage level in a few clock cycles when the processor emerges from a “sleep” state and enters a “computing” state. The use of additional copper and the need for specific circuit board design serves to increase the cost and complexity of using the base board to supply power.

#In the course of this detailed description, the reference will be frequently made to the attached drawings in which:

#FIG. 1 is a schematic view of a typical pinout arrangement used for a processor;

#FIG. 2 is an elevational diagrammatic view of a typical prior art power delivery system to a processor accommodated in a PGA socket;

#FIG. 1 illustrates a typical pinout arrangement 20 as is found in an array-type processor package. This package would typically include a socket surrounding the pin arrangement 20 and a plurality of conductive contacts 21-23 located therein. Each of these contacts has two opposing ends, with one set of ends, that visible in FIG. 1 and being the top ends that protrude into the socket for contact to opposing traces, leads, balls, etc. On the bottom of the chip package, the other set of end that extend out from the socket. As seen in FIG. 1, the pinout locations include signal locations 21, power locations 22 and ground, or power return, locations 23. As can be seen in FIG. 1, there are a number of pins that are associated with the power aspect. The use of the present invention permits the elimination of a significant number of the power pins in such an array so that they may be freed for use with other signal aspects of the processor.

#FIG. 2 illustrates a known power delivery system to a pin grid array (“PGA”) in which a voltage regulator module (“VRM”) 25 in mounted on a circuit board 26 and which is connected to one or more conductive traces 27a, 27b that are interconnected to the VRM and which typically will serve as “power out” and “power return” paths which are respectively indicated in FIG. 2 by the (+) and (−) designations. A socket 28 having a plurality of LGA contacts 29 may be mounted to the circuit board 26. A processor 30 includes a semiconductor die 31 mounted to a package 32 and may include contacts such as BGA contacts 33 disposed thereon that serve to connect the package 32 to a substrate, shown as a circuit board 36 which in turn has a series of conductive pins 36 thereon, typically arranged in the pattern of FIG. 1.

#In such a prior art system, the VRM 25 takes up valuable space on the circuit board 26 and the use of conductive traces 27a, 27b within the circuit board 256 can increase the cost of the overall system.