Bounce tolerant fuse trimming circuit with controlled timing

A trimming circuit for modifying electronic circuits, the trimming circuit comprising:

• a first input pad configured to receive a trigger signal;
• a delay transistor configured to couple between a first voltage potential and an output node, the delay transistor having a delay gate coupled to the first input pad, the delay gate being a first delay structure configured to add a first delay to the trigger signal and to filter power and voltage spikes in the trigger signal, the first delay being of a sufficiently long duration so as to decrease the switching speed of the delay transistor and to allow the delay gate to filter power and voltage spikes in the trigger signal;
• and
• a trimming fuse having a first end and a second end, the first end being coupled with the output node, the second end being configured to receive a second voltage potential, wherein the delay transistor supplies sufficient current to trim the trimming fuse when the delay transistor turns on, and wherein the trimming fuse decouples the output node from the second end when the trimming fuse is trimmed.

A method for modifying an electrical circuit, the method comprising:

• providing a trimming fuse between at least two circuit nodes;
• providing a transistor to supply sufficient current to trim the trimming fuse when the transistor turns on;
• receiving a trigger signal to turn on the transistor;
• delaying the rise time of the trigger signal for a sufficiently long duration so as to decrease the switching speed of the delay transistor and to filter power and voltage spikes in the trigger signal;
• and
• decoupling the circuit nodes when the trimming fuse is trimmed.

A delay transistor comprising:

• a substrate;
• a plurality of conduction channels embedded in the substrate;
• a plurality of active regions embedded in the substrate, the active regions alternating with the conduction channels;
• a source contact coupled with first alternating active regions;
• a drain contact coupled with second alternating active regions;
• and
• a gate structure overlaying the conduction channels, the gate structure being configured to receive an input signal, wherein the gate structure is a single gate structure, and wherein the gate structure provides an RC delay to the input signal and filters power and voltage spikes in the input signal, the RC delay being of a sufficiently long duration so as to decrease the switching speed of the transistor and allow the gate structure to filter power and voltage spikes.

A delay pad structure comprising:

• a substrate;
• an active region embedded in the substrate, and active region being configured to receive an input signal, the active region having a serpentine shape, the active region providing an RC delay to the input signal and filtering power and voltage spikes in the input signal;
• and
• a plurality of diodes coupled with the active region, the diodes being reversed biased, wherein the diodes provide additional capacitance to the RC delay.

A delay line structure comprising:

• a substrate;
• a thin oxide layer coupled onto a first side of the substrate, the thin oxide layer having a square shape;
• a polysilicon layer coupled onto the thin oxide layer, the polysilicon layer being configured to receive an input signal, the combination of the thin oxide layer coupled between the substrate and the polysilicon layer providing an RC delay to the input signal and filtering power and voltage spikes in the input signal;
• and
• a plurality of diodes coupled with the polysilicon layer, the diodes being reversed biased, wherein the diodes provide additional capacitance to the RC delay.