High resolution, high speed, low power switched capacitor analog to digital converter

An analog to digital converter to convert an analog input signal to a digital output signal, the converter comprising:

• a first converter segment having a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode coupled to a first common node and a second electrode coupled through respective controllable switches to either one of a first reference voltage terminal and an input terminal at which the input signal is to be received;
• a second converter segment having a second array of binary weighted capacitors with respective capacitances that are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode coupled to a second common node and a second electrode coupled through respective controllable switches to either one of said first reference voltage terminal and said input terminal;
• a coupling capacitor with a first electrode coupled to the first common node and a second electrode coupled to the second common node;
• a comparator having a first terminal coupled to the second common node, a second terminal coupled to a second reference voltage terminal, and third terminal;
• a control unit coupled to the controllable switches of the first and second converter segments to selectively open or close the controllable switches and to produce the digital output signal based on a signal received from the third terminal of the comparator;
• and
• a capacitance element permanently connected between the first common node and a third reference voltage terminal, wherein the coupling capacitor and the capacitance element have capacitances, Cs and CATT respectively, that substantially satisfy a relationship:
• (2p−1)·Cs−CATT=2p·C, where p is a number of bits coded in the first converter segment and C is the unit capacitance.