Efficient data-directed scrambler for noise-shaping mixed-signal converters

A data-directed scrambler for processing digital signals having a structured equally-weighted code, wherein bits of the code that are constrained to be all on or all off are assigned to bit groups, comprising:

• inputs for receiving N bits of an input signal having the structured equally-weighted code;
• outputs for supplying N scrambled bits of an output signal;
• and
• two or more scrambler columns connected in series between said inputs and said outputs, each of said scrambler columns including at least one swapper cell, wherein bit groups of the structured equally-weighted code are input to respective scrambler columns in accordance with the number of bits in the bit groups.

A method for processing digital signals having an unequally-weighted code, comprising the steps of:

• providing a data-directed scrambler including inputs for receiving unequally-weighted bits of an input signal, outputs for supplying N scrambled bits of an output signal, and two or more scrambler columns connected in series between said inputs and said outputs, one or more of said scrambler columns including a swapper cell and a digital fanout;
• supplying least significant bits in the unequally-weighted code to a swapper cell;
• and
• supplying higher order bits in the unequally-weighted code to respective digital fanouts.

A digital-to-analog converter comprising:

• a data-directed scrambler for processing a digital signal having an unequally-weighted code, comprising inputs for receiving unequally-weighted bits of an input signal, outputs for supplying N scrambled bits, and two or more scrambler columns connected in series between said inputs and said outputs, one or more of said scrambler columns including a swapper cell and a digital fanout, wherein least significant bits in the unequally-weighted code are input to a swapper cell and higher order bits in the unequally-weighted code are input to respective digital fanouts;
• a digital-to-analog converter circuit including N equally-weighted digital-to-analog converter elements for converting the scrambled bits to respective analog values;
• and
• a summing circuit for summing said analog values to produce an analog output that represents the digital signal.

A digital-to-analog converter comprising:

• a code converter for converting a digital input to a structured equally-weighted code, wherein bits of the code that are constrained to be all on or all off are assigned to bit groups;
• a data-directed scrambler for processing digital signals having the structured equally-weighted code, comprising inputs for receiving N bits of a digital signal having the structured equally-weighted code, outputs for supplying N scrambled bits, and two or more scrambler columns connected in series between said inputs and said outputs, each of said scrambler columns including at least one swapper cell, wherein bit groups of the structured equally-weighted code are input to respective scrambler columns in accordance with the number of bits in the bit groups;
• a digital-to-analog converter circuit including N equally-weighted digital-to-analog converter elements for converting the scrambled bits to respective analog values;
• and
• a summing circuit for summing said analog values to produce an analog output that represents the digital input.

An analog-to-digital converter comprising:

• a summing unit for subtracting a feedback signal from an analog input signal and providing a summing unit output;
• a loop filter for receiving said summing unit output and providing a filter output signal;
• a multi-bit quantizer for providing a digital output in response to said filter output signal;
• and
• a digital-to-analog converter responsive to said digital output for providing said feedback signal to said summing unit, said digital-to-analog converter comprising:
• a data-directed scrambler for processing a digital signal having an unequally-weighted code, comprising inputs for receiving unequally-weighted bits of said digital output, outputs for supplying N scrambled bits, and two or more scrambler columns connected in series between said inputs and said outputs, one or more of said scrambler columns including a swapper cell and a digital fanout, wherein least significant bits in the unequally-weighted code are input to a swapper cell, and higher order bits in the unequally-weighted code are input to respective digital fanouts;
• a digital-to-analog converter circuit including N equally-weighted digital-to-analog converter elements for converting the scrambled bits to respective analog values;
• and
• a summing circuit for summing said analog values to produce said feedback signal, wherein the digital output of said multi-bit quantizer represents the analog input signal.