Reponse-based analog-to-digital conversion apparatus and method

An apparatus for increased analog-to-digital conversion resolution, the apparatus comprising:

• a comparator bank configured to compare an analog signal with a plurality of reference voltages and thereby provide a plurality of comparison signals;
• a digital encoder configured to convert the plurality of comparison signals to digital values comprising a plurality of bits;
• and
• a response-based interpolator configured to sample the digital values and to estimate at least one additional bit based on the settling characteristics of the digital values.

An apparatus for increased analog-to-digital conversion resolution, the apparatus comprising:

• a comparator bank configured to compare an analog signal with a plurality of reference voltages to provide a plurality of comparison signals;
• a digital encoder configured to convert the plurality of comparison signals to digital values comprising a plurality of bits including a least significant bit;
• and
• a settling-pattern interpolator configured to exclusively sample the least significant bit and to conduct an exclusive OR comparison of an early and a late sample of the least significant bit to provide at least one additional bit to the digital values.

An apparatus for increased analog-to-digital conversion resolution, the apparatus comprising:

• a comparator bank configured to compare an analog signal with a plurality of reference voltages to provide a plurality of comparison signals;
• a digital encoder configured to convert the plurality of comparison signals to digital values comprising a plurality of bits including a least significant bit;
• and
• a settling-time interpolator configured to detect the settling time of the least significant bit to provide at least one additional bit to the digital values.

A method for increased analog-to-digital conversion resolution, the method comprising:

• converting an analog signal to digital values comprising a plurality of bits;
• sampling the digital values;
• and
• estimating at least one additional bit based on the settling characteristics of the digital values.

A method for increased analog-to-digital conversion resolution, the method comprising:

• converting an analog signal to digital values comprising a plurality of bits, including a least significant bit;
• sampling the least significant bit;
• and
• conducting an exclusive OR comparison of an early and a late sample of the least significant bit to provide at least one additional bit to the digital values.

A method for increased analog-to-digital conversion resolution, the method comprising:

• converting an analog signal to digital values comprising a plurality of bits, including a least significant bit;
• sampling the least significant bit;
• and
• detecting the settling time of the least significant bit to provide at least one additional bit to the digital values.

A method for increased analog-to-digital conversion resolution, the apparatus comprising:

• comparing an analog signal with a plurality of reference voltages to provide a plurality of binary comparison signals;
• encoding the plurality of binary comparison signals to provide digital values comprising a plurality of bits;
• sampling the digital values;
• and
• estimating at least one additional bit based on the settling characteristics of the digital values.

A method for increased analog-to-digital conversion resolution, the method comprising:

• comparing an analog signal with a plurality of reference voltages to provide a plurality of binary comparison signals;
• encoding the plurality of binary comparison signals to provide digital values comprising a plurality of bits including a least significant bit;
• sampling the least significant bit of the digital values;
• and
• conducting an exclusive OR comparison of an early and a late sample of the least significant bit to provide at least one additional bit to the digital values.

A method for increased analog-to-digital conversion resolution, the method comprising:

• comparing an analog signal with a plurality of reference voltages to provide a plurality of binary comparison signals;
• encoding the plurality of binary comparison signals to provide digital values comprising a plurality of bits including a least significant bit;
• sampling the least significant bit of the digital values;
• and
• detecting the settling time of the least significant bit to provide at least one additional bit to the digital values.