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AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsChoon-Beng Sia, Kiat Seng Yeo, Toe Naing Swe, Cheng Yeow Ng, Alex See
Estimating the term…
A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecting the center proximate ends of the plurality of turns and a second plurality of vias connecting the center distal ends of the plurality of turns. A first connecting portion connects to the center proximate ends of the plurality of turns and a second connecting portion connecting to the center distal end of the plurality of turns. A dielectric material contains the inductor.
A method of manufacturing a parallel stacked inductor comprising:
A method of manufacturing a parallel spiral stacked inductor comprising:
A parallel stacked inductor comprising:
A parallel spiral stacked inductor comprising:
A parallel stacked inductor comprising:
A parallel spiral stacked inductor comprising:
Dependencies are inferred from the claim text.
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Resistors, capacitors or inductors: inductors
Printed inductances: with stacked layers
Integrated devices formed in or on semiconductor substrates that comprise only semiconducting
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes: inductive…
Term end not estimated
The present invention relates generally to integrated circuits and more particularly to on-chip silicon-based inductors.
Increasing demands for personal mobile communications equipment have motivated recent research activities to focus on the development of inexpensive, small size, low power consumption, and low noise level systems. To satisfy these requirements, one of the most important and indispensable circuit components is the on-chip silicon-based inductor.
As a result, miniaturization of the inductor on silicon has become a current key research area and extensive work has been done in this area. However, despite efforts by many researchers having skill in the art, achieving high performance on-chip inductors, i.e., high qualify factor (Q), still remains a major problem especially when radio frequency integrated circuits (RFICs) are built on silicon.
FIG. 1 (PRIOR ART) is a cross-sectional view of a prior art on-chip inductor along line 1-1 of FIG. 2 (PRIOR ART);
FIG. 2 (PRIOR ART) is a cross-sectional view of the prior art on-chip inductor along line 2-2 of FIG. 1 (PRIOR ART);
FIG. 3 is shown a cross-sectional view of a parallel spiral stacked inductor of the present invention along line 3-3 of FIG. 4; and
Referring now to FIG. 1 (PRIOR ART), therein is shown a cross-sectional view of a prior art on-chip inductor 10 along line 1-1 of FIG. 2 (PRIOR ART). A substrate 12, of a material such as silicon, has a plurality of dielectric layers formed thereon of a material such as silicon dioxide. Sequentially, a field dielectric layer 14 (such as a field oxide), a connecting interlayer dielectric (ILD) layer 16 (such as a silicon oxide), a first level ILD layer 18, and a second level ILD layer 20 are formed over the substrate 12. Embedded within the dielectric layers is a spiral stacked inductor 22.
The term “over” as used in herein is defined vertically above a horizontal plane parallel to the conventional surface of a wafer on which the on-chip inductor is formed regardless of the orientation of the wafer. Terms, such as “on”, “below”, “higher”, “lower”, “above”, and “under”, are defined with respect to the horizontal plane.
The term “processed” or “forming” as used herein to refer to the formation of vias and turns includes conventional semiconductor deposition of photoresist, hard and soft mask photolithography, etch, and strip, as appropriate.