Lock detector for phase locked loops

#The present invention relates generally to lock detectors for phase lock loops and, more particularly, to a lock detector which establishes upper and lower bounds to a lock range in order to ensure that phase error is substantially confined within the range before acquisition of lock is declared.

#Phase lock loops (PLLs) and clock recovery circuits (CRCs) have found wide application in such diverse areas as digital communication systems, wireless systems, digital circuits and data recovery systems for use in connection with mass storage media such as hard disk, tape and optical drives. In the field of digital communication systems, phase lock loops are typically used in modern digital communications receivers to recover useful data from a transmission signal stream by providing data recovery circuitry with a timing reference having the appropriate frequency and phase characteristics so as to match timing characteristics of the transmitted signal and thus, ensure proper data recovery.

#In modern HDTV signal transmissions, a receiver must be capable of locking onto a transmitter's pilot carrier phase as well as the transmitter's timing phase. Locking the receiver to the transmitter's carrier phase is commonly referred to as carrier phase recovery, whereas locking onto the timing phase of the transmitter is referred to as timing phase recovery. Both of these functions are critical to a modern day communications system since the receiver must be synchronized to the transmitter in order that transmitted data may be correctly demodulated, and equalized.

#These and other features, aspects and advantages of the present invention will be more fully understood when considered with respect to the following detailed description, appended claims and accompanying drawings wherein:

#FIG. 1(a) is a semi-schematic block level diagram of a conventional phase lock loop (PLL) system used for data recovery, according to the prior art;

#FIG. 1(b) is a waveform diagram illustrating the frequency and phase error response of the PLL of FIG. 1(a) to an input frequency step;

#Conceptually, a conventional phase lock loop (PLL), such as depicted in semi-schematic block diagram form in FIG. 1(a), is a feedback system that operates on the excess phase of nominally periodic signals. Implementation of such a PLL normally comprises a phase detector (PD) or phase and frequency detector (PFD) 10 whose output is coupled to a loop filter (low-pass filter or LPF) 12 which, in turn, drives some means for generating a synchronous clock signal 14, such as a voltage controlled oscillator (VCO), current controlled oscillator (CCO) or decision controlled oscillator (DCO). When receiving data, during what is conventionally termed frequency or velocity lock, the oscillation frequency of the clock signal generator (termed a VCO for convenience) is determined by, and locked to the frequency of an external periodic signal source provided for such purpose (not shown), just prior to receiving an input datastream. Once frequency or velocity lock is established, the VCO runs in what might be termed a quasi-flywheel mode at a mean frequency determined during velocity lock.

#Subsequent correction control to the VCO frequency is developed by phase-locking a transition edge of the synchronous VCO signal to a transition edge of an incoming data signal. The VCO is phase-locked to the incoming serial data stream by comparing the phase of the rising edge of the VCO clock signal FIG. 1 to the phase of the rising edge of data in the phase detector 10. A phase or time difference detected between the two rising edges causes the phase detector to issue a signal proportional to the phase difference which directs the VCO to either speed-up or slow-down in response to phase variations in the datastream.

#Conventionally, the phase detector incorporates logic circuitry (in effect a logical NOR function) which precludes an output signal from being issued during phase comparisons unless two phase edges are present during a particular comparison cycle. This features prevents the PLL from becoming unstable by trying to perform a phase comparison between a VCO rising edge and a, for example, data ZERO bit (a data signal necessarily without a rising edge).