Coarse tuning for fractional-n synthesizers

#The present invention relates in general to fractional-N synthesizers, and, in particular, to a technique to provide coarse tuning of an oscillator in a fractional-N synthesizer.

#Frequency synthesizers are used in many systems, including microprocessors and radio frequency (RF) communication systems. Frequency synthesizers of the phase locked loop (PLL) type contain controlled oscillators (CO) that are typically current controlled oscillators (ICO) or voltage controlled oscillators (VCO). The output of the CO is often used as an injection signal for an RF mixer or in a microprocessor clock system. The frequency synthesizer controls the CO such that its frequency or period is approximately equal to that of a stable frequency reference multiplied by a predetermined ratio. In many applications, there is a need to compensate for process and environmental variations that affect synthesizer performance. The prior art contains many systems that compensate for variations in the CO's frequency tuning range or center frequency by performing a coarse tuning of the tunable elements in the CO. These systems have been developed for integer-N synthesizers where the divided CO signal used for feedback to the phase detector has a steady period when the CO's output frequency is not changing.

#The use of fractional-N synthesizers provides reduced lock times for the synthesizer's phase lock loop (PLL) and improves noise performance, but introduces significant jitter on the divided CO signal. Even with a constant CO output frequency, the divider modulus is constantly changing to provide a desired average fractional modulus over a period of time. The jitter on the divided CO signal significantly reduces the accuracy of existing techniques for calibrating and tuning the CO. Accordingly, there is a need for a technique to reduce the impact of jitter on the divided CO signal and provide accurate calibration or coarse tuning of a CO in a fractional-N synthesizer in a cost-effective and efficient manner.

#The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.

#FIG. 1 is a block representation of a fractional-N synthesizer according to one embodiment of the present invention.

#FIG. 2A is a schematic representation of a resonant tank circuit of a voltage controlled oscillator according to one embodiment of the present invention.

#The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

#With reference to FIG. 1, a fractional-N frequency synthesizer 10 is illustrated according to one embodiment of the present invention. The synthesizer 10 includes a fractional-N phase lock loop (PLL) 12 and coarse tuning circuitry 14. The PLL 12 generates a desired frequency for the output signal, FVCO, 16, of a voltage controlled oscillator (VCO) 18. In traditional fashion, the output signal FVCO 16 is also provided to divider circuitry 20 to divide the output signal FVCO by a factor N to produce a divided VCO signal FV, which is fed to one of two inputs of a phase detector 22.

#A reference signal, FREF, 24, is divided by a factor R by divider circuitry 26 to produce a divided reference signal, FR, which is provided to the other input of the phase detector 22. The N and R factors are selected so that the frequencies of the divided reference signal, FR, and the divided VCO signal, Fv are equal when the desired output signal, FVCO, 16, is at a desired frequency. The phase detector 22 compares the relative phases of the divided reference signal, FR, and the divided VCO signal, FV, and provides an output relative to the difference in phase to control the VCO 18. The output of the phase detector is preferably provided by a charge pump and filtered by a loop filter 28 to provide a stable voltage for a VCO fine tuning signal, VT, to adjust the desired output frequency FVCO of the VCO 18 based on the difference in phase of the divided reference signal, FR, and the divided VCO signal, FV.