Low-voltage booster circuits and methods of operation thereof

#This application claims priority from Korean Patent Application No. 2002-20888, filed on Apr. 17, 2002, the contents of which are herein incorporated by reference in their entirety.

#The present invention relates to semiconductor integrated circuit devices, and, more particularly, to booster circuits for semiconductor integrated circuit devices.

#As lower power consumption has been desired in semiconductor integrated circuit devices, power supply voltage has been increasingly lowered to provide lower power consumption. However, semiconductor memory devices often include circuits that need voltages higher than the power supply voltage. For this reason, booster circuits are often included in semiconductor integrated circuit devices to provide higher voltages.

#FIG. 1 is a circuit diagram of a conventional booster circuit;

#FIG. 2 is a schematic diagram of a booster circuit according to some embodiments of the present invention;

#FIG. 3 shows exemplary waveforms of control signals for the circuit of FIG. 2;

#The present invention now will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout.

#FIG. 2 illustrates a booster circuit 10 according to some embodiments of the present invention. FIG. 3 shows waveforms of control signals of the booster circuit 10 of FIG. 2. FIG. 4A is a diagram showing voltages of respective nodes of the booster circuit in a charge period, FIG. 4B is a diagram showing voltages of respective nodes of the present booster circuit in a pump period, and FIG. 4C is a diagram showing voltages of respective nodes of the present booster circuit before the node are charged.

#Referring to FIG. 2, in the booster circuit 10, one terminal of a capacitor C10 is coupled to a node ND1, which may be selectively coupled to a ground node GND via a switch SW10 responsive to a control signal P1 and to a power supply node VCC via a switch SW20 responsive to a control signal P2. The other terminal of the capacitor C10 is coupled to a node ND2, which may be selectively coupled to a node ND3 via a switch SW30 responsive to the control signal P1 and to a high voltage terminal VP via a switch SW40 responsive to the control signal P2. The node ND3 may be selectively coupled to the power supply node VCC via a switch SW60 responsive to the control signal P2. A capacitor C20 is coupled between the node ND3 and a node ND4. The node ND4 may be selectively coupled to a high voltage terminal VP via a switch SW50 responsive to the control signal P2 and to the power supply node VCC via a switch SW70 responsive to the control signal P1. Herein, the signals P1 and P2 are oscillating signals having non-overlapping “high” levels, as illustrated in FIG. 3.