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AssigneeInternational Business Machines Corporation
InventorsDouglas W. Stout, Scott T. Wameling, Charles H. Windisch JR.
Estimating the term…
An integrated circuit comprising a first circuit powered by a first power supply. The first circuit sends a first signal referenced to the voltage of the first power supply to a second circuit powered by a second power supply. The second circuit receives the first signal and converts the first signal to a second signal of the same logical value as the first signal and is referenced to the voltage of the second power supply.
An integrated circuit comprising:
An integrated circuit comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Interface arrangements: of complementary type, e.g. CMOS
Pulse technique
Term end not estimated
1. Field of the Invention
The present invention relates to the field of integrated circuits; more specifically, it relates to the communication circuits in integrated circuit chips containing voltage islands.
2. Background of the Invention
The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic representation of a semiconductor device according to the present invention;
FIG. 2 is a schematic diagram of a differential driver circuit according to the present invention;
VDDX (where X is an integer) is defined as the power supply voltages supplied only to corresponding voltage islands X and may represent the same or different voltages. VDDG is defined as a global voltage supplied to some or all of the voltage islands as well as non-voltage island portions of the chip. VDDG may be different from or equal to any given VDDX. Fencing is defined as the operation of holding outputs of a sending voltage island or inputs of a receiving voltage island at a known voltage while VDDX of the sending voltage island is off or sequencing on or off. VDDG is always powered as long as at least one voltage island is powered.
FIG. 1 is a schematic representation of a semiconductor device according to the present invention. FIG. 1 presents an illustrative example only and an unlimited number of variations are possible. In FIG. 1, chip 100 includes a first voltage island 105, a second voltage island 110, a third voltage island 115, global logic 120 and a plurality of I/O drivers 125. The present invention is not limited to three voltage islands. Semiconductor chip 100 may contain only one voltage island or as many voltage islands as the design of chip 100 requires.
First voltage island 105 includes a differential driver 130, a fence 0 single ended driver 135, a fence 1 single-ended driver 140 and a fence hold single-ended driver 145. Differential driver 130 is illustrated in FIG. 2 and described infra. Fence 0 single ended driver 135 is illustrated in FIG. 7 and described infra. Fence 1 single-ended driver 140 is illustrated in FIG. 8 and described infra. Fence hold single-ended driver 145 is illustrated in FIG. 9 and described infra.