Conditional clock buffer circuit
AssigneeBroadcom Corporation
InventorBrian J. Campbell
Life of this patent
Estimating the term…
Abstract
A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.
Claims20
A conditional clock buffer circuit having a clock output and coupled to receive a clock input and a condition signal, the conditional clock buffer circuit comprising:
- a first circuit coupled to receive the clock input, the first circuit configured to generate a first state on the clock output responsive to a first phase of the clock input;
- and
- a second circuit coupled to receive the clock input and the condition signal, wherein the second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input.
A clock tree comprising:
- one or more levels of buffering coupled to receive an input clock and output a buffered clock;
- and
- one or more conditional clock buffer circuits coupled to receive the buffered clock and a condition signal, each conditional clock buffer circuit having a clock output and including:
- a first circuit coupled to receive the buffered clock, the first circuit configured to generate a first state on the clock output responsive to a first phase of the buffered clock;
- and
- a second circuit coupled to receive the buffered clock and the condition signal, wherein the second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the buffered clock.
A computer accessible medium comprising one or more data structures representing:
- a first circuit coupled to receive a clock input, the first circuit configured to generate a first state on a clock output responsive to a first phase of the clock input;
- and
- a second circuit coupled to receive the clock input and a condition signal, wherein the second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input.
The computer accessible medium as recited in claim 20 wherein the one or more data structures further represent a latch circuit coupled to the first circuit and coupled to the clock output, wherein the latch circuit is configured to hold the clock output during a remaining portion of the second phase.
Dependencies are inferred from the claim text.