Sequential activation delay line circuits and methods

#This application claims the benefit of Korean Patent Application No. 2002-21680, filed Apr. 19, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.

#The present invention relates to the field of delay line circuits such as Delay Locked Loops (DLLs), and more particularly, to delay line control circuits and methods for DLLs.

#In integrated circuit chip Dynamic Random Access Memories (DRAMs), the skew of a clock signal in the integrated circuit chip may affect the operation of the DRAM. A DLL circuit may be used as a compensator for skew of an internal clock signal in a DRAM and/or other integrated circuit chips. The structure and operation of DLLs is well known to those having skill in the art and are described, for example, in U.S. Pat. Nos. 6,459,314; 6,452,432; 6,434,083; 6,388,485; 6,366,148; 6,285,225; 6,222,894; 6,101,137; 5,901,190; and 5,880,612, all of which are assigned to the assignee of the present application.

#FIG. 1 is a block diagram of a conventional delay line control circuit with a delay locked loop (DLL);

#FIG. 2 is a logic diagram of control signals used to control unit delay cells shown in FIG. 1;

#FIG. 3 illustrates an internal circuit of a unit delay cell shown in FIG. 1;

#The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

#FIG. 4 is a block diagram of a delay line circuit according to some embodiments of the present invention. Referring to FIG. 4, a delay line circuit 400 according to some embodiments of the present invention includes a delay line portion 410 and a control portion 420.

#The delay line portion 410 includes a series, for example, first through N-th (where N is an integer) unit delay cells DC1, DC2, . . . , and DCN. A respective one of the delay cells includes an input and an output that are sequentially connected, such that an output of a preceding unit cell is connected to an input of a succeeding delay cell. More specifically, in some embodiments, each of the unit delay cells DC1, DC2, . . . , and DCN receives outputs at the previous terminal, delays the output for a predetermined amount of time and outputs a delayed value. An internal clock signal INTCK is input to the first unit delay cell DC1.