Method of performing duty cycle correction

#This invention relates to the fields of duty cycle correction and differential pair circuits, and, more specifically, to methods of performing duty cycle correction, including but not limited to methods of performing duty cycle correction using differential pair circuits.

#Many non-linear systems introduce into a sinusoidal signal non-linearities in the form of high frequency harmonics, each at an integer multiple of the fundamental frequency. The harmonics may be odd harmonics, i.e., harmonics the frequency of which is an odd integer multiple of the fundamental frequency, even harmonics, i.e., harmonics the frequency of which is an even integer multiple of the fundamental frequency, or both.

#The introduction of even harmonics to sinusoidal signals is problematic in differential or balanced applications where it is desired to maintain odd symmetry. The reason is the non-uniform group delay, i.e., a delay which varies with frequency, typically exhibited by many transmission media delays higher frequency components of a signal more than the fundamental frequency. Because of this non-uniform group delay, transmission of the signal through the media delays the even harmonics in the sinusoidal signal more than the fundamental frequency, thus destroying the odd symmetry exhibited by the signal.

#The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.

#FIGS. 1 and 2 are examples illustrating how the addition to a sinusoidal signal having a uniform duty cycle of a delayed even harmonic introduces a non-uniform duty cycle.

#FIG. 3 illustrates a core portion of a bipolar implementation of a capacitor-degenerating differential pair circuit.

#As utilized herein, terms such as “about” and “substantially” are intended to allow some leeway in mathematical exactness to account for tolerances that are acceptable in the trade, e.g., any deviation upward or downward from the value modified by “about” or “substantially” by any value in the range(s) from 1% to 20% of such value.

#Referring to FIG. 3, an implementation of the core portion of a capacitor-degenerating differential pair circuit is illustrated. In this particular implementation, the circuit comprises a differential pair of NPN transistors, identified with numerals 302a and 302b, with a capacitor 310 coupled between the emitters of the two transistors. Each of the emitters is coupled to a current source, identified respectively with numerals 304a and 304b, which in turn is coupled to ground. Each of the current sources 304a and 304b source a current Io. A voltage-mode differential input signal, VIN+ and VIN−, is input to the bases of the two transistors, identified respectively with numerals 306a and 306b (and with the labels ‘A’ and ‘B’). In addition, a differential current mode output signal, IOUT+ and IOUT−, is produced on terminals 308a and 308b (identified respectively with labels ‘C’ and ‘D’).

#While this particular implementation involves the use of bipolar NPN transistors, a differential voltage mode input signal, a differential current mode output signal, and a single capacitor between the emitters of the two transistors, it should be appreciated that the invention is not so limited and that embodiments of a capacitor degenerating differential pair circuit are possible for use in connection with the invention which involve the use of technologies other than bipolar, including but not limited to FET, MOS, or CMOS technology, that involve the use of PNP bipolar, FET, MOS, or CMOS transistors, that involves a single ended input signal or an input signal which is current mode rather than voltage mode, that involves a single ended output signal or an output signal which is voltage mode rather than current mode, or that involves more than one capacitor coupled between the emitters (or drains) of the differential pair of transistors.