Clock distribution network using feedback for skew compensation and jitter filtering

#The present invention relates generally to clock distribution in integrated circuits (ICs) and, more specifically, relates to a clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering.

#High-performance and very large scale integration chips such as microprocessors, chipsets, system on-chips, application specific integrated circuits (ASICs) and digital signal processing (DSP) systems, are typically provided with a large number of sequential elements that perform various logic functions, such as mathematic operations. A clock signal, known as a “global” clock signal, may be used as a timing reference to synchronize data or logic operations performed by these elements positioned at different locations (points), or destinations, on the chip.

#A major challenge in such circuit designs is to distribute a “global” clock signal to the elements through different interconnect segments across the chip with minimal clock inaccuracy, particularly when the operating frequency of the chip and the frequency of the “global” clock signal are high. Clock inaccuracy often results in one clock edge not arriving at a sampling point on the chip at its nominal time, measured relative to another clock edge. One type of clock inaccuracy is commonly referred to as clock “skew”. Clock “skew” within a chip is the difference in time that the “global” clock signal reaches different locations (points) on the chip. There are a number of factors for causing clock “skew”, including, for example, electromagnetic propagation delays, buffer delays in the distribution network, resistive-capacitive (RC) delays associated with various distribution lines in the distribution network, and variations in the manufacturing process, temperature gradients, power supply and load capacitance. Another type of clock inaccuracy is referred to as clock “jitter”. Clock “jitter” is the distortion in clock cycle and phase difference accumulated over time (distance), and can be exacerbated by variations caused by noise.

#A better understanding of the present invention will become apparent from the following detailed description of example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the following written and illustrated disclosure focuses on disclosing example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and that the invention is not limited thereto. The spirit and scope of the present invention are limited only by the terms of the appended claims. The following represents brief descriptions of the drawings, wherein:

#FIG. 1 illustrates a semi-distributed architecture for an example clock distribution network according to an example embodiment of the present invention;

#FIG. 2 illustrates an example clock processor node of the clock distribution network shown in FIG. 1;

#Before beginning a detailed description of the subject invention, mention of the following is in order. When appropriate, like reference numerals and characters may be used to designate identical, corresponding or similar components in differing figure drawings. Further, in the detailed description to follow, example sizes/values/ranges may be given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that IC chips of smaller size can be manufactured. In addition, well known power/ground connections to IC chips and other components may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details.

#Various example embodiments of the present invention are applicable for use with all types of semiconductor IC chips, including, but not limited to, high-frequency microprocessors, chipsets, system on-chips, application specific integrated circuits (ASICs), digital signal processing (DSP) systems and other types of programmable logic arrays or devices that need a clock signal for distribution to multiple elements on a single chip or multiple chips in a package, such as, for example, a system having a plurality of dice including a microprocessor in communication with other dice including chipset and memory devices.

#Attention now is directed to the drawings and particularly to FIG. 1, in which a semi-distributed architecture for clock distribution according to an embodiment of the present invention is illustrated. As shown in FIG. 1, the semi-distributed architecture 100 utilizes a global clock distribution network 110 driven by a single clock generator/synchronizer in the form of a master phase-locked loop (PLL) 120 to feed an array of slave PLLs kept synchronized using variable-delay elements (VDEs) at respective peripheral clock processor nodes 130A-130N (where N refers to any number of peripheral nodes in the global clock distribution network 110) distributed throughout the area of an IC die.