On chip timing adjustment in multi-channel fast data transfer

#1. Field of the Invention

#The present invention generally relates to chip timing adjustment and more particularly to a chip timing adjustment structure which is implemented by programmable delay units and configuration word settings.

#2. Description of the Related Art

#The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment(s) of the invention with reference to the drawings, in which:

#FIG. 1(a) is a schematic diagram of a conventional circuit that requires timing adjustment;

#FIG. 1(b) is a schematic diagram illustrating the two controllers communicating through fast data buses, transmitter, transmission line and receiver;

#As mentioned above, even if the chips of a driver or receiver have excellent stand-alone timing performances (and good jitter budgets) when they are mounted on the PCB, serious timing problems could still exist because of driver and receiver chip processing variances, noise, and/or different microstrip line channel lengths. The invention described below overcomes these problems with a novel chip timing adjustment structure which is implemented by programmable delay units and configuration word settings. Thus, the invention provides a solution of “on-chip” timing adjustment using programmable delay units and configuration word settings.

#Referring now to FIG. 1(a), a system block diagram is shown. More specifically, FIG. 1(a) shows the block diagram of a receiver having N parallel channels 110-112. Good timing results are required, not only for the input bit signal and clock of each channel, but also among the outputs of all channels. Due to the noise jitters, procession variation and the length difference of PCB microstrip or stripline, without the invention shown below, it is very difficult to meet the designer's timing requirement in the structure shown in FIG. 1(a).

#FIG. 1(b) shows two controllers 250, 251 controlling, respectively, a transmitter 260 and a receiver 261 that communicate over transmission lines 266. The fast data communication, such as 40 Gb/s from the controller 250 to the controller 251, is through the transmitter 260, the transmission lines 266, and the receiver 261. In FIG. 1(c), a slow serial communication data and clock signal line 265 is shown in addition to the relatively faster data bases 267. The relatively slower data/clock signal line 265 allows the receiver 263 to include programmable delay units, which allows the invention to adjust signal delay properties “on-chip” and on-line, as discussed in greater detail below.