Gate driver for MOS control semiconductor devices

#The present invention generally relates to a semiconductor power converting apparatus with employment of semiconductor elements and the like. More specifically, the present invention is directed to a semiconductor power converting apparatus capable of suppressing an occurrence of an overvoltage while a switching operation is carried out.

#As disclosed in IPEC2000 S-17-3 “Development of IGBT series and Parallel Connection Technology for High Power Converters”, each of arms of a power converter constituted by a series connection of MOS control semiconductors such as IGBTs, so that an MOS control semiconductor power converter for outputting a high AC voltage and a high DC voltage can be realized. Since the MOS control semiconductor elements which are series-connected to each other and constitute each of these arms are turned ON, or OFF at the same time in response to a pulse signal controlled by either the PWM control or the PAM control, the DC voltage may be converted into the AC voltage and/or the AC voltage may be converted into the DC voltage.

#On the other hand, another technique is opened by which the MOS control semiconductors series-connected to each other, which constitute the respective arms, may be protected from overvoltages. The published abstract of the Japanese Electric Society Industrial Application Department Meeting in 1999, vol. 2, entitled “Switching Test of Flat-pack IGBTs connected in Series”, pp. 119-120 describes the following protection technique. That is, the avalanche element is connected between the gate and the collector of the IGBT, while the avalanche element is brought into the conductive state when this avalanche element exceeds a predetermined voltage and thus avalanches. The voltage of the avalanche element is also increased in connection with the increase of the collector voltage the IGBT. When this voltage of the avalanche element exceeds the avalanche voltage of the avalanche element, the current is supplied from the collector of the IGBT to the gate thereof via this avalanche element, so that the gate voltage of the IGBT is increased so as to lower the impedance of the IGBT. As a result, the collector voltage of the IGBT is suppressed in order that the IGBT can be protected from the element destruction (breakdown) by applying the overvoltage to this IGBT. Also, this publication entitled “Switching Test for Series-Connection of Planar IGBTs”, vol. 2 (1999) of the lecture on Japanese Electric Society Industrial Application Department discloses that the MOS control semiconductors can be protected in such a manner that the gate voltage is increased so as to increase the saturated current value.

#FIG. 1 is a circuit diagram of schematically showing a major unit of one arm of a power converter according to an embodiment 1 of the present invention.

#FIG. 2 is a graph for graphically indicating a characteristic of an IGBT employed in a semiconductor power converting apparatus of the present invention.

#FIG. 3 is an explanatory diagram for explaining a series-connection of MOS control semiconductors having different saturated currents from each other.

#Referring now to drawings, various embodiments of the present invention will be described in detail. It should be understood that the same reference numerals will be employed as those for indicating the circuit elements having the same functions in the respective embodiments. It should also be noted that potentials appeared at the respective terminals of an IGBT 11 to an IGBT 14, and also potentials within gate circuits are defined, while an emitter potential of each to these IGBTs is used as a reference. In other words, it is so assumed that a collector potential of the IGBT 11 corresponds to a collector-to-emitter voltage of the IGBT 11, whereas a collector potential of the IGBT 12 corresponds to a collector-to-emitter voltage of the IGBT 12. It should also be noted that even when an IGBT is replaced by another MOS control semiconductor device such as an MOSFET, a similar effect to that of the below-mentioned embodiment may be achieved.

#Embodiment 1

#An arrangement of a semiconductor power converting apparatus according to this embodiment 1 of the present invention will now be described with reference to FIG. 1 and FIG. 4. FIG. 4 schematically shows a major unit of the semicondcutor power converting apparatus according to this embodiment 1, and FIG. 1 schematically represents a major unit of an arm 20 shown in FIG. 4. In the power converting apparatus of FIG. 4, three sets of two series-connected arms 20 are connected in a parallel manner, and these arms 20 are connected to a DC voltage source 21. Each of neutral points of the paired arms is connected to a load 22.