Semiconductor logical operation circuit

#The present invention relates generally to a semiconductor logical operation circuit, and more particularly to a circuit suited for reducing a consumption of electric power.

#A semiconductor integrated circuit is, with downsizing and a decrease in weight of devices using the semiconductor integrated circuit, highly required to reduce its electric power consumption. One of effective schemes of reducing the electric power consumption is to decrease the power consumption when the circuit is in a non-operation state.

#For instance, one example of a conventional dynamic logical operation circuit is that a selection signal and a clock signal are ANDed. If a selection signal SEL assumes a high-level, a logical output node is set in a precharge state when a clock input CLK is at a low-level and set in an operation state when the clock input CLK is at a high-level, and, if the selection signal SEL assumes the low-level, the logical output node keeps its level high, i.e., the precharge state irrespective of the input of the logical operation circuit. This scheme reduces the power consumption by stopping a futile operation as on standby, i.e., during a non-operation.

#FIG. 1 is a circuit diagram showing a first embodiment of the present invention;

#FIG. 2 is a circuit diagram showing a modified example of the embodiment shown in FIG. 1; and

#FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

#Embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

#FIG. 1 is a diagram showing a circuit in a first embodiment of the present invention.

#This circuit is defined as an AND circuit, wherein NMOS transistors Q1, Q2, of which gates receive an input A and an input B respectively, are connected in series, this AND circuit outputting a logical product thereof. The transistor Q1 is connected to a power supply via a PMOS transistor Q3 for precharge, which is connected in series to the transistor Q1. Further, the transistor Q2 is grounded via an NMOS transistor Q4 connected in series to the transistor Q2.