Dynamic scan circuitry for b-phase

A clock buffer circuit comprising:

• a series connection of transistors coupled between a first node and ground, the series connection of transistors including at least a first transistor and a second transistor, wherein the first transistor has a first control node coupled to receive a first signal corresponding to a functional clock and the second transistor has a second control node;
• a logic circuit coupled to the second control node and coupled to receive the first signal and a first input;
• and
• a third transistor coupled to the first node and having a third control node coupled to receive a second input.

In an apparatus including a first dynamic logic circuit having an output node on which a scan value is provided during scan and one or more second dynamic logic circuits, wherein one of the second dynamic logic circuits has an input coupled to the output node of the first dynamic logic circuit, the method comprising:

• generating at least one evaluate pulse on a first clock controlling at least evaluation of the second dynamic logic circuits;
• isolating the output node of the first dynamic logic circuit from inputs to the first dynamic logic circuit using the second clock and the third clock responsive to a scan mode signal indicating that scan is active, the second clock controlling precharge of the first dynamic logic circuit and the third clock controlling evaluation of the first dynamic logic circuit;
• and
• sampling the output of the second dynamic logic circuits subsequent to generating the at least one evaluate pulse, the output responsive to the scan value on the output node of the first dynamic logic circuit.