Method and apparatus for universal program controlled bus architecture

A method of providing an integrated circuit, comprising:

• providing a first programmable logic array comprising a plurality of program controlled cells and programmable interconnections to perform programmable logic functions;
• providing a first megacell comprising a plurality of logic cells and interconnections to perform a specified logic function, said plurality of logic cells and interconnections being non-programmable;
• and
• providing a first logic controlled three-statable cell, wherein said first programmable logic array communicates with said first megacell through logic control using said first logic controlled three-statable cell.

An integrated circuit, comprising:

• a first programmable logic array comprising a plurality of program controlled cells and programmable interconnections after fabrication to perform programmable logic functions;
• a first megacell comprising a plurality of logic cells and interconnections to perform a specified logic function, said plurality of logic cells and interconnections being non-programmable;
• and
• a first plurality of conductors, wherein said first programmable logic array and said first megacell are configured to communicate with each other through a first conductor of said first plurality of conductors, wherein said first programmable logic array is configured to send a first signal to said first megacell through said first conductor using a first switch and said first megacell is configured to send a second signal to said first programmable logic array through said first conductor using a second switch.

A method of providing an integrated circuit, comprising:

• providing a first programmable logic array comprising a plurality of program controlled cells and programmable interconnections after fabrication to perform programmable logic functions;
• providing a first megacell comprising a plurality of logic cells and interconnections to perform a specified logic function, said plurality of logic cells and interconnections are non-programmable;
• and
• providing a first plurality of conductors, wherein said first programmable logic array and said first megacell communicate with each other through a first conductor of said first plurality of conductors, wherein said first programmable logic array sends a first signal to said first megacell through said first conductor using a first switch and said first megacell sends a second signal to said first programmable logic array through said first conductor using a second switch.

An electronic system, comprising:

• a first plurality of conductors, said first plurality of conductors organized parallel along a first dimension;
• a first logic controlled three-stable cell, wherein said first logic controlled three-statable cell is configured to selectively drive a first conductor of said first plurality of conductors through a first switch without requiring traversal of another conductor;
• and
• said first logic controlled three-statable cell is configured to selectively drive a second conductor of said first plurality of conductors through a second switch without requiring traversal of another conductor.

A method of providing an electronic system, comprising:

• providing a first plurality of conductors, said first plurality of conductors organized parallel along a first dimension;
• providing a first logic controlled three-stable cell, wherein said first logic controlled three-statable cell selectively drives a first conductor of said first plurality of conductors through a first switch without requiring traversal of another conductor;
• and
• said first logic controlled three-statable cell selectively drives a second conductor of said first plurality of conductors through a second switch without requiring traversal of another conductor.