Fault tolerant semiconductor system

A connection test method which is used for a semiconductor system in which a plurality of semiconductor chips are interconnected via wirings, the plurality of semiconductor chips including a connection rearrange wiring section configured by a plurality of blocks each including a connection test circuit and connection rearrange circuit, and a connection test control circuit including a test data generating circuit which generates test data and a coincidence determination circuit which detects whether or not poor connection occurs, and the connection test circuit including a test data storage element which stores test data and a test result storage element which stores the test result and making a connection test for the wirings at the time of boot by control of the connection test control circuit, comprising:

• initializing the test result storage elements in the connection test circuits,
• generating test data by use of the test data generating circuit, writing the test data into the test data storage elements connected via scan paths,
• transferring and writing test data between the test data storage elements of the plurality of semiconductor chips via the wirings between the semiconductor chips,
• sequentially reading out values of the test data storage elements provided in the blocks of the plurality of semiconductor chips via the scan paths and sequentially writing the results of coincidence determination made by the coincidence determination circuit into the test data storage elements,
• recording the results of the connection tests stored in the test data storage elements into the test result storage elements of the respective blocks,
• repeatedly performing an operation of said recording of the test data to said recording of the test result into the test result storage elements with respect to a required test pattern,
• writing values of the test data storage elements into the test result storage elements of the respective blocks, and
• transferring the test result written into the test result storage element to the connection test control circuit via the scan path to determine pass/fail of the connection.

A semiconductor system manufacturing method comprising:

• forming first semiconductor elements in a first wafer,
• dividing the first wafer into a discrete form to form a plurality of first semiconductor chips,
• forming second semiconductor elements in a second wafer,
• dividing the second wafer into a discrete form to form a plurality of second semiconductor chips,
• interconnecting the first and second semiconductor chips to each other by use of a first group of wirings and a second group of wirings for redundancy and mounting the second semiconductor chip on the first semiconductor chip,
• making a connection test for the first group of wirings which connect the first and second semiconductor chips, and
• making unusable a wiring of the first group in which poor connection occurs and rearranging the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test.

A semiconductor system manufacturing method comprising:

• forming semiconductor elements in a wafer,
• dividing the wafer into a discrete form to form a plurality of semiconductor chips,
• connecting at least one of the semiconductor chips thus formed to a first group of wirings and a second group of wirings for redundancy of a wiring board and mounting the semiconductor chip thereon,
• making a connection test for the first group of wirings which connect the semiconductor chip to the wiring board, and
• making unusable a wiring of the first group in which poor connection occurs and rearranging the connection between the semiconductor chip and the wiring board by use of the second group of wirings when the poor connection is detected in the wiring of the first group by the connection test.

A semiconductor system manufacturing method comprising:

• forming semiconductor elements in a wafer,
• dividing the wafer into a discrete form to form a plurality of semiconductor chips,
• connecting at least one of the semiconductor chips thus formed to a first group of leads and a second group of leads for redundancy of a TAB tape and mounting the semiconductor chip thereon,
• making a connection test for connection between the semiconductor chip and the first group of leads of the TAB tape, and
• making unusable a lead of the first group in which poor connection occurs and rearranging the connection between the semiconductor chip and the TAB tape by use of the lead of the second group when the poor connection is detected in the lead of the first group by the connection test.