Frequency sesing NMOS voltage regulator
AssigneeMicron Technology, Inc.
InventorsKent M. Kalpakjian, John D. Porter
Life of this patent
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Abstract
A frequency sensing NMOS voltage regulator is disclosed. A NMOS source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a PMOS switching transistor, and a source connected to a load. The gate of the PMOS transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the PMOS transistor, the amount of current produced by the NMOS transistor is made a function of the cycle rate of the system clock and the current provided by the NMOS transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.
Claims66
A voltage regulator comprising:
- a first transistor having a gate, a first terminal and a second terminal, said second terminal for providing a regulated voltage to a load;
- a second transistor having a gate, a first terminal for connection to a supply voltage, and a second terminal connected to said first terminal of said first transistor;
- and
- a delay circuit having an input coupled to a clock signal and an output, said output being connected to said gate of said second transistor,
- wherein said second transistor is turned on and off in response to the output of said delay circuit to regulate the supply of current from a supply voltage at said first terminal of said second transistor to said second terminal of said first transistor.
An integrated circuit comprising:
- a synchronous circuit in which a load current varies linearly with a clock frequency;
- and
- a voltage regulator to supply a regulated voltage to said synchronous circuit, said voltage regulator comprising:
- a first transistor having a gate, a first terminal and a second terminal, said synchronous circuit being connected to said second terminal;
- a second transistor having a gate, a first terminal for connection to a supply voltage, and a second terminal connected to said first terminal of said first transistor;
- and
- a delay circuit having an input coupled to a clock signal and an output, said output being connected to said gate of said second transistor,
- wherein said second transistor is turned on and off in response to the output of said delay circuit to regulate the supply of current from a supply voltage at said first terminal of said second transistor to said second terminal of said first transistor.
A processing system comprising:
- a processing device which processes data;
- a synchronous circuit connected to said processing device, said synchronous circuit having a load current which varies linearly with a clock frequency;
- and
- a voltage regulator to supply a regulated voltage to said synchronous circuit, said voltage regulator comprising:
- a first transistor having a gate, a first terminal and a second terminal, said synchronous circuit being connected to said second terminal;
- a second transistor having a gate, a first terminal for connection to a supply voltage, and a second terminal connected to said first terminal of said first transistor;
- and
- a delay circuit having an input coupled to a clock signal and an output, said output being connected to said gate of said second transistor,
- wherein said second transistor is turned on and off in response to the output of said delay circuit to regulate the supply of current from a supply voltage at said first terminal of said second transistor to said second terminal of said first transistor.
A method of regulating voltage comprising:
- passing a clock signal through a delay circuit to produce a delay signal;
- providing said delay signal to a transistor;
- using said delay signal to turn on and off said transistor;
- and
- regulating current passed through said transistor to a load by said turning on and off of said transistor in response to said delay signal.
Dependencies are inferred from the claim text.