Design of interconnection pads with separated probing and wire bonding regions
AssigneeKulicke & Soffa Investments, Inc.
InventorPaul T. Lin
Life of this patent
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Abstract
The present invention provides a solution to the problem of weakening bond integrity in integrated circuit devices due in part to test probes galling and weakening the interconnect pads during functional and reliability test probing. In doing so, the invention enables a lowering of the chance a bond wire or interconnect pad will be lifted during a wire bonding process or in normal operation of an integrated circuit device.
Claims25
An integrated circuit having an interconnect region, the interconnect region comprising:
- an interconnect pad having a first portion and a second portion;
- and
- a dielectric passivation layer overlying portions of the integrated circuit device, the dielectric passivation layer having a first opening corresponding to and exposing the first portion of the interconnect pad, and a second opening corresponding to and exposing the second portion of the interconnect pad;
- wherein a portion of the dielectric passivation layer overlies a portion of the interconnect pad between the first portion and the second portion.
2 The integrated circuit of claim 1 wherein the first portion of the interconnect pad is a wire bonding portion and the second portion of the interconnect pad is a probing portion.
4 The integrated circuit of claim 3 wherein the second portion of the interconnect pad overlies an active region of the integrated circuit device.
An integrated circuit having an interconnect region, the interconnect region comprising:
- an interconnect pad having a first portion and a second portion;
- and
- a visible indicator indicating a division between the first portion and the second portion;
- wherein the visible indicator is an etched portion of the interconnect pad.
9 The integrated circuit of claim 8 wherein the second portion of the interconnect pad overlies an active region of the integrated circuit device.
10 The integrated circuit of claim 7 wherein the first portion of the interconnect pad is a wire bonding portion and the second portion of the interconnect pad is a probing portion.
An integrated circuit having an interconnect region, the interconnect region comprising:
- an interconnect pad having a first portion and a second portion;
- a visible indicator indicating a division between the first portion and the second portion;
- and
- a dielectric passivation layer having an opening that exposes both the first and second portions of the interconnect pad.
14 The integrated circuit of claim 12 wherein the second portion of the interconnect pad overlies an active region of the integrated circuit device.
An integrated circuit having an interconnect region, the interconnect region comprising:
- an interconnect pad having a first portion and a second portion;
- a visible indicator indicating a division between the first portion and the second portion;
- and
- a dielectric layer surrounding a portion of the interconnect pad, wherein the visible indicator is an etched portion of the dielectric layer.
19 The integrated circuit of claim 17 wherein the second portion of the interconnect pad overlies an active region of the integrated circuit device.
A method comprising:
- forming an interconnect pad on an integrated circuit device, the interconnect pad having a first portion and a second portion,
- probing the second portion of the interconnect pad;
- and
- bonding a bond wire to the first portion of the interconnect pad.
Dependencies are inferred from the claim text.