Low profile stack semiconductor package

A low profile stack semiconductor package, comprising:

• a substrate;
• a lower chip having an active surface formed with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein the non-active surface is mounted on the substrate, and a cushion member is formed at a peripheral edge on the active surface of the lower chip;
• a plurality of lower bonding wires for electrically connecting the lower chip to the substrate in a manner that, the lower bonding wires extend from the bond pads of the lower chip in a direction substantially parallel to the active surface of the lower chip, and reach the cushion member beyond which the lower bonding wires turn to be directed toward the substrate, wherein the lower bonding wires are free of forming wire loops as extending above the active surface of the lower chip, and the cushion member is interposed between the lower bonding wires and the lower chip, allowing the lower bonding wires to be free of contact with the lower chip;
• an adhesive applied over the active surface of the lower chip, for encapsulating the bond pads, the cushion member, and part of the lower bonding wires extending above the lower chip;
• an upper chip having an active surface with a plurality of centrally-situated bond pads thereon, and a non-active surface opposed to the active surface, wherein the non-active surface is mounted on the adhesive and a cushion member is formed at a peripheral edge on the active surface of the upper chip;
• a plurality of upper bonding wires for electrically connecting the upper chip to the substrate in a manner that, the upper bonding wires extend from the bond pads of the upper chip and reach the cushion member, beyond which the upper bonding wires turn to be directed toward the substrate, wherein the cushion member is interposed between the upper bonding wires and the upper chip, allowing the upper bonding wires to be free of contact with the upper chip;
• an encapsulate for encapsulating the lower and upper chips, and the lower and upper bonding wires;
• and
• a plurality of solder balls implanted on the substrate and used to outside of the encapsulant, for electrically connecting the lower and upper chips to an external device.