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AssigneeInternational Business Machines Corporation
InventorsCharles R. Davis, David L. Hawken, Dae Young Jung, William F. Landers, David L. Questad
Estimating the term…
A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.
A semiconductor device, comprising:
A semiconductor device, comprising:
A method of forming a reinforcement structure for a semiconductor device having multilayer wiring levels with at least some of said wiring levels employing a low-k dielectric insulating material there between, said method comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Structural arrangements therefor: interconnections for measuring or testing, e.g. probe pads
Characterised by their conductive parts: vias, e.g. via plugs
Characterised by their insulating parts: insulating materials thereof
Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps: bond pads specially adapted therefor
Term end not estimated
1. Field of the Invention
The present invention relates to a multilayer wiring arrangement and, more particularly, to a multilayer semiconductor structure and method of forming said structure which acts to suppress delamination and cracking of low dielectric constant interlayer insulating materials.
2. Background and Related Art
FIG. 1 shows a diagrammed sketch of a photograph showing delamination and cracking in a device using low-k dielectric material.
FIG. 2 shows a top view of a corner area of a device with wire bond pads.
FIG. 3 shows a top view of a corner area of a device with flip chip solder bumps.
In the diagrammed sketch of a photograph showing delamination and cracking of FIG. 1, substrate 1, such as silicon, is shown supporting a multilayer wiring structure with layers of insulating material, including a low-k dielectric insulating material and copper metallurgy therebetween. Substrate 1 includes active components covered by an inorganic insulating material. Metal lines 3 and 5, such as copper lines, are separated by a layer of low-k dielectric material, such as SiLK™. Similarly, metal lines 5 and 9 are separated by a layer of low-k dielectric material 13. In like manner, metal lines 9 and 11 are separated by a layer of low-k material 15. Layer 17 is an oxide dielectric material covered with passivation layer 19.
As further shown in FIG. 1, a series of cracks 21, 23, 25 and 27 have occurred due to any of a variety of stress factors, such as, the stresses caused by thermal cycling. Since the CTE of low-k dielectric material is significantly different than that of silicon and its oxides, thermal cycling causes a different expansion rates at the interfaces to thereby induce stresses therein. Similarly, the lower modulus of elasticity, toughness and adhesion characteristics of low-k dielectric materials tends to compound the problem. As seen in FIG. 1, crack 21 extends through low-k dielectric insulating material 7 and is a result of delamination of such material in the vicinity of the crack. Similar delamination of insulating materials has occurred in the vicinity of cracks 23, 25 and 27.
FIG. 2 shows a partial top view of a semiconductor chip 29 employing wire bond pads 31 around the periphery for I/O interconnection to and from active device region 32. Also shown in the peripheral region 33 exterior to the pads, is the mesh-like reinforcing interconnection structure 35, in accordance with the present invention. As shown, the interconnection structure comprises bridged metal lines 37 extending around the periphery of the chip 29 exterior to pads 31. Metal lines 37 are bridged by metal lines 38. This line structure is repeated at lower levels and the various levels are interconnected by conductive vias. It should be noted that the drawings shown herein are not to scale but are merely provided to facilitate an understanding of the invention.