Structure of integrated trace of chip package
AssigneeFairchild Semiconductor Corporation
InventorsRajeev Joshi, Chung-Lin Wu
Life of this patent
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Abstract
A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.
Claims20
A semiconductor die package comprising:
- (a) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;
- (b) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;
- (c) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;
- (d) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer;
- and
- (e) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer.
A method comprising:
- (a) providing a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;
- (b) forming a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;
- (c) forming an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;
- (d) forming a single dielectric layer over the underbump metallurgy layer, wherein the single dielectric layer comprises a second aperture on and in direct contact with the underbump metallurgy layer;
- and
- (e) forming a solder structure on the underbump metallurgy layer and within the second aperture of the dielectric layer.
An electrical assembly comprising:
- (a) a circuit substrate including a plurality of conductive regions;
- and
- (b) a semiconductor die package comprising (i) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side, (ii) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture, (iii) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad, (iv) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer, and (v) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer,
- wherein the solder structure is coupled to a conductive region within the plurality of conductive regions.
Dependencies are inferred from the claim text.