Structure and fabrication method of electrostatic discharge protection circuit
AssigneeUnited Microelectronics Corp.
InventorsShiao-Shien Chen, Tsun-Lai Hsu, Tien-Hao Tang, Hua-Chou Tseng
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Abstract
A structure of an electrostatic discharge protection circuit, using a deep trench structure to replace the guard ring at a periphery of the electrostatic discharge protection circuit. Consequently, the device area is smaller compared to the device with the guard ring. Moreover, the device area is further reduced because the distance between the transistors of the electrostatic discharge protection circuit is shortened. At the same time, the functions of latch-up immunity and substrate noise immunity are more effective.
Claims18
A structure of an electrostatic discharge protection circuit, comprising:
- a substrate;
- a deep trench isolation layer, formed in the substrate;
- an N well, formed in the substrate and using the deep trench isolation layer to isolate from other devices;
- a P well, formed in the substrate and using the deep trench isolation layer to isolate from other devices;
- a PMOS transistor, formed in the N well and comprising a PMOS gate, a PMOS drain and a PMOS source;
- an N+ pick up region, formed in the N well;
- a first isolation layer, in the N well to isolate the N+ pick up region, and the PMOS transistor;
- a second isolation layer, in the N well to isolate the N+ pick up region and the deep trench isolation layer;
- an NMOS transistor, formed in the P well and comprising an NMOS gate, an NMOS drain and an NMOS source;
- a P+ pick up region, formed in the P well;
- a third isolation layer, in the P well to isolate the P+ pick up region and the NMOS transistor;
- a fourth isolation layer, in the P well to isolate the P+ pick up region and the deep trench isolation layer;
- and
- a buried layer, formed in the N well.
A method of fabricating an electrostatic discharge protection circuit, comprising:
- providing a substrate in which an N well and a P well are formed;
- forming a buried layer in the N well;
- forming a deep trench isolation layer in the substrate, wherein the deep trench isolation layer isolates the P well, the N well and other devices;
- simultaneously forming a PMOS gate on the N well and an NMOS gate on the P well;
- forming a PMOS source and a PMOS drain in the N well at two sides of the PMOS gate, and an P+ pick up region in the P well;
- and
- forming an NMOS source and an NMOS drain in the P well at two sides of the NMOS gate, and a N+ pick up region in the N well.
A method of fabricating a BiCMOS device with an electrostatic discharge protection circuit, the method comprising:
- providing a substrate in which the substrate is separated into an ESD region, a bipolar region and a CMOS region, wherein the ESD region has a first N well and a first P well, the CMOS region has a second N well and a second P well and the bipolar region has a third N well;
- simultaneously forming a first buried layer at a horizontal junction between the first N well and the substrate, and a second buried layer in the third N well;
- forming a deep trench isolation layer in the substrate, wherein the deep trench isolation layer isolates the first P well, the first N well and other devices, and also isolates the second P well, the second N well, the third N well and other devices;
- simultaneously forming a first PMOS gate on the first N well and an first NMOS gate on the first P well, a second PMOS gate on the second N well and an second NMOS gate on the second P well, and a conductive layer on the third layer;
- simultaneously forming a first PMOS source and a first PMOS drain in the first N well at two sides of the first PMOS gate, and a first N+ pick up region in the first N well, a second PMOS source and a second PMOS drain in the second N well at two sides of the second PMOS gate, and an second N+ pick up region in the second N well;
- simultaneously forming a first NMOS source and a first NMOS drain in the first P well at two sides of the first NMOS gate, and a first P+ pick up region in the first N well, and a second NMOS source and a second NMOS drain in the second P well at two sides of the second NMOS gate, and a second P+ pick up region in the second N well;
- and
- forming a bipolar transistor on the conductive layer.
Dependencies are inferred from the claim text.