Lateral type power MOS transistor and fabrication method thereof

A lateral type power MOS transistor comprising:

• a support substrate;
• a buried insulating film formed on said support substrate;
• a semiconductor layer of a first conductivity type formed on said buried insulating film;
• a groove formed in said semiconductor layer of said first conductivity type;
• a base region of a second conductivity type formed from a surface of said semiconductor layer of said first conductivity type adjacent to one of side walls of said groove to a depth substantially equal to a depth of said groove;
• a high impurity density source region of said first conductivity type formed from a surface of said base region and extending in a depth direction of said base region adjacent to one of said side walls of said groove, an impurity density of said high impurity density source region being higher than that of said semiconductor layer;
• a low impurity density region of the other conductivity type formed between said base region and said buried insulating film, an impurity density of said low impurity density region being lower than that of said base region;
• a drain region of said first conductivity type formed from a surface of said semiconductor layer on the other side wall of said groove and extending in a depth direction thereof, an impurity density of said drain region being higher than that of said semiconductor layer;
• a gate insulating film formed in said groove;
• a gate electrode formed on said gate insulating film within said groove and opposing to said base region;
• and
• a PN junction formed by said low impurity density region and said semiconductor layer, one end of said PN junction being in contact with said groove and the other end of said PN junction being in contact with said buried insulating film.