Clock distribution networks and conductive lines in semiconductor integrated circuits

An integrated circuit comprising:

• a semiconductor substrate having a trench therein;
• and
• a conductive line formed in the trench and interconnecting two laterally spaced nodes of the integrated circuit.

A manufacturing method comprising manufacturing a first semiconductor integrated circuit comprising a first surface and a second surface that are opposite to each other, wherein the first semiconductor integrated circuit comprises a clock distribution network having an input contact pad at the second surface and having a plurality of output contact pads at the first surface.

A method comprising:

• providing a clock signal to an input contact pad of a clock distribution network formed in a first semiconductor integrated circuit;
• the clock distribution network coupling the clock signal to output contact pads, wherein the output contact pads are located at a first surface of the first integrated circuit and the input contact pad is located at a second surface of the first integrated circuit, the second surface being opposite to the first surface;
• wherein the output contact pads are bonded to contact pads of a second semiconductor integrated circuit.

A manufacturing method comprising:

• forming a trench in a semiconductor substrate;
• and
• forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry.