Semiconductor device having transistor and method of manufacturing the same

A method of manufacturing a semiconductor device comprising:

• forming a portion having gate electrodes including gate electrode tops, etch mask layers, spacers formed of a material having a low dielectric constant at sidewalls of the gate electrodes and the etch mask layers, and transistors having source/drain regions formed in the semiconductor substrate and inbetween the gate electrodes;
• forming another portion having conductive patterns and an interlevel dielectric layer formed of a material having an excellent etching selectivity to the etch mask layers to fill spaces inbetween the conductive patterns;
• and
• forming an etch stopper extending between the spacers and the sidewalls of the gate electrodes and the etch mask layers from adjacent the semiconductor substrate to adjacent the gate electrode tops.

A method of manufacturing a semiconductor device comprising:

• forming a semiconductor substrate having a cell area and a peripheral circuit area;
• forming gate electrodes including gate electrode tops and etch mask layers sequentially formed in the cell area and the peripheral circuit area in the semiconductor substrate;
• forming spacers formed of a material having a low dielectric constant at sidewalls of the gate electrodes and the etch mask layers and formed in at least one of the cell area and the peripheral circuit area;
• forming etch stoppers extending between the spacers and the sidewalls of the gate electrodes and the etch mask layers from adjacent the semiconductor substrate to adjacent the gate electrode tops;
• forming a conductive layer filling spaces between the gate electrodes in the cell area;
• and
• forming an interlevel dielectric layer filling spaces between the gate electrodes in the peripheral circuit area and formed of a material having an excellent etching selectivity to the etch mask layers.

A method of manufacturing a semiconductor device comprising:

• forming a semiconductor substrate;
• forming gate electrodes on the semiconductor substrate including gate electrode tops;
• forming a spacer on a sidewall of at least one of the gate electrodes;
• and
• forming an etch stopper extending between the spacers and the sidewalls of the gate electrodes from adjacent the semiconductor substrate to adjacent the gate electrode tops.