Methods for fabricating field effect transistors having elevated source/drain regions

#The present invention relates to integrated circuit devices and fabrication methods thereof, and more particularly, to field effect transistor (FETs) and fabrication methods for field effect transistors.

#As the integration density of integrated circuits continues to increase, the size of Field Effect Transistors (FET), such Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), implemented in such integrated circuits may also decrease. However, a decrease in the size of a MOSFET may reduce the MOSFET's channel length. As appreciated by those skilled in the art, a reduction in the MOSFET's channel length may cause a “short channel effect” (SCE) which may increase the likelihood of a phenomenon known as “punch through” between a source and a drain of the MOSFET.

#Short channel effects may arise when the depletion region widths of the source and drain junctions become comparable to the channel length. As a result, the potential distribution in the channel may become two-dimensional which can result in large values of sub-threshold current, a decrease in threshold voltage, and/or non-saturation of drain current due to punch through. Punch through may occur when the sum of the source and drain depletion widths exceed the channel length, thereby causing the channel to be punched through (i.e., the depletion region punches through the neutral n-region) when voltage is applied. Thus, since “short channel effects” may complicate device operation and may degrade device performance, it may be desirable to reduce these effects.

#FIG. 1 is a cross-sectional view of an FET having an elevated source/drain structure for explaining problems with a conventional process of fabricating the same; and

#FIGS. 2 through 7 are cross-sectional views of FETs according to embodiments of the invention during intermediate fabrication steps.

#The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.

#The present invention can be realized in other manners without departing from the spirit and indispensable features of the present invention. For example, in a preferred embodiment, a gate pattern is formed by sequentially stacking a gate oxide film, a gate electrode and a capping layer and forming a gate spacer on the sidewalls of the stacked layer. A gate pattern mentioned in the present specification is used in the broadest meaning, and is not restricted to specific shapes as described in the following preferred embodiments. Also, in the preferred embodiment, the capping layer in the gate stack is an oxide film, but can be replaced by a dielectric film. Alternatively, a capping layer does not have to be utilized. A dielectric film for a gate spacer can also be replaced by another film material. Therefore, the contents described in the preferred embodiment are just examples, and do not limit the present invention.

#Referring to FIG. 2, an isolation film 102 is formed on an integrated circuit substrate, such as a silicon semiconductor substrate, by a typical method. A gate stack may include a gate oxide film 104, a gate electrode 106 and/or a capping layer 108 is formed on an active region defined by the isolation film 102. The gate electrode 106 can be formed of doped polysilicon, and the capping layer 108 can be an oxide layer or a multiple layer including an oxide layer. Then, a Lightly Doped Drain (LDD) region having a shallow junction is formed on the surface of the integrated circuit substrate by performing primary ion implantation using the gate stack as an ion implantation mask.