High-voltage vertical transistor with a multi-layered extended drain structure

#The present invention relates to semiconductor devices fabricated in a silicon substrate. More specifically, the present invention relates to field-effect semiconductor transistor structures capable of withstanding high voltages.

#High-voltage, field-effect transistors (HVFETs) are well known in the semiconductor arts. Most often, HVFETs comprise a device structure that includes an extended drain region that supports the applied high-voltage when the device is in the “off” state. HVFETs of this type are commonly used in power conversion applications such as AC/DC converters for offline power supplies, motor controls, and so on. These devices can be switched at high voltages and achieve a high blocking voltage in the off state while minimizing the resistance to current flow in the “on” state. The blocking or breakdown voltage is generally denoted as Vbd. The acronym Rsp refers to the product of the resistance and surface area, and is generally used to describe the on-state performance of the device. An example of a prior art HVFET having an extended drain region with a top layer of a conductivity type opposite that of the extended drain region is found in U.S. Pat. No. 4,811,075.

#In a conventional HVFET the extended drain region is usually lightly doped to support high voltages applied to the drain when the device is off. The length of the extended drain region is also increased to spread the electric field over a larger area so the device can sustain higher voltages. However, when the device is on (i.e., conducting) current flows through the extended drain region. The combined decrease in doping and increase length of the extended drain region therefore have the deleterious effect on the on-state performance of the device, as both cause an increase in on-state resistance. In other words, conventional high-voltage FET designs are characterized by a trade-off between Vbd and Rsp.

#The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:

#FIG. 1 is a cross-sectional side view of a vertical high-voltage, field-effect transistor (HVFET) device structure in accordance with one embodiment of the present invention.

#FIG. 2 is a cross-sectional side view of one embodiment of a lateral HVFET fabricated in accordance with the present invention.

#A high-voltage field-effect transistor having an extended drain or drift region and a method for making the same is described. The HVFET has a low specific on-state resistance and supports high voltage in the off-state. In the following description, numerous specific details are set forth, such as material types, doping levels, structural features, processing steps, etc., in order to provide a thorough understanding of the present invention. Practitioners having ordinary skill in the semiconductor arts will understand that the invention may be practiced without many of these details. In other instances, well-known elements, techniques, and processing steps have not been described in detail to avoid obscuring the invention.

#FIG. 1 is a cross-sectional side view of a vertical n-channel (i.e., NMOS) HVFET 20 in accordance with one embodiment of the present invention. It should be understood that the elements in the figures are representational, and are not drawn to scale in the interest of clarity. It is also appreciated that a p-channel transistor may be realized by utilizing the opposite conductivity types for all of the illustrated diffusion/doped regions. Furthermore, although the figure appears to show two separate devices, those of skill will understand that such transistor structures are commonly fabricated in an annular, inter-digitated, or otherwise replicated manner.

#The device structure of FIG. 1 includes an insulated-gate, field-effect transistor (IGFET) having a gate 30 (comprised, for example, of polysilicon), and a gate-insulating layer 29 that insulates gate 30 from the underlying semiconductor regions. Gate-insulating layer 29 may comprise ordinary silicon dioxide or another appropriate dielectric insulating material. The extended drain region of vertical HVFET 20 comprises two or more parallel N-type drift regions 22 situated between p-type body regions 26 and extending down to the N+ substrate 21. For instance, FIG. 1 shows drift region 22a extending from beneath gate oxide 29a between P-body regions 26a & 26b down to N+ substrate 21. Similarly, drift region 22b extends from gate oxide 29b between P-body regions 26c & 26d down to N+ substrate 21.