Nonvolatile memory cell with low doping region
AssigneeAltera Corporation
InventorsChristopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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AssigneeAltera Corporation
InventorsChristopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
Estimating the term…
A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
A nonvolatile memory cell comprising:
Dependencies are inferred from the claim text.
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Structural details of configuration resources: for memories
Arranged in matrix form: the logic functions being realised by the interconnection of rows and columns
Arranged in matrix form: structural details of routing resources
Arranged in matrix form: structural details for adapting physical parameters
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The present invention relates to the field of the integrated circuit fabrication. More specifically, the invention provides a technique of fabricating a nonvolatile memory device for an integrated circuit, where the nonvolatile memory device has reduced substrate hot electrons.
Interconnect is a fundamental component of integrated circuits. Interconnect is used to couple the elements, components, circuits, and signals in an electronic system together in order to perform functions. For example, interconnect is used to supply power to the electronic components. Interconnect is also used to implement analog and digital functions in electronic systems. Interconnect, especially programmable or configurable interconnect, is especially useful in particular applications, such as, but not limited to, programmable logic devices (PLDs) where it is desirable for interconnections to be programmably determined. Other applications may include microprocessors, memories, and application specific integrated circuits (ASICs), to name a few.
PLDs are well known to those in the electronic art. Programmable logic devices are commonly referred to as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs, PLDs, EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic™, and MAX® 5000, MAX® 7000, and FLEX® 8000 EPLDs made by Altera Corp.
FIG. 1 is a block diagram of a digital system incorporating a programmable logic device integrated circuit;
FIG. 2A is a block diagram showing an architecture for a programmable logic device;
FIG. 2B is a block diagram showing an architecture for a programmable logic device;
FIG. 1 shows a block diagram of a digital system within which the present invention may be embodied. The system may be provided on a single board, on multiple boards, or even within multiple enclosures. FIG. 1 illustrates a system 101 in which a programmable logic device 121 may be utilized. Programmable logic devices (sometimes referred to as a PALs, PLAs, FPLAs, PLDs, EPLDs, EEPLDs, LCAs, or FPGAs), are well known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices allow a user to electrically program standard, off-the-shelf logic elements to meet a user's specific needs. See, for example, U.S. Pat. No. 4,617,479, incorporated herein by reference for all purposes. Such devices are currently represented by, for example, Altera's MAX® series of PLDs and FLEX® series of PLDs. The former are described in, for example, U.S. Pat. Nos. 5,241,224 and 4,871,930, and the Altera Data Book, June 1996, all incorporated herein by reference. The latter are described in, for example, U.S. Pat. Nos. 5,258,668, 5,260,610, 5,260,611, and 5,436,575, and the Altera Data Book, June 1996, all incorporated herein by reference for all purposes. Logic devices and their operation are well known to those of skill in the art.
In the particular embodiment of FIG. 1, a processing unit 101 is coupled to a memory 105 and an I/O 111 and incorporates a programmable logic device (PLD) 121. PLD 121 may be specially coupled to memory 105 through connection 131 and to I/O 111 through connection 135. The system may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems may be designed for a wide variety of applications such as, merely by way of example, telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, and others.
Processing unit 101 may direct data to an appropriate system component for processing or storage, execute a program stored in memory 105 or input using I/O 111, or other similar function. Processing unit 101 may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, programmable logic device programmed for use as a controller, or other processing unit. Furthermore, in many embodiments, there is often no need for a CPU. For example, instead of a CPU, one or more PLDs 121 may control the logical operations of the system. In some embodiments, processing unit 101 may even be a computer system. Memory 105 may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage retrieval means, or any combination of these storage retrieval means. PLD 121 may serve many different purposes within the system in FIG. 1. PLD 121 may be a logical building block of processing unit 101, supporting its internal and external operations. PLD 121 is programmed to implement the logical functions necessary to carry on its particular role in system operation.