A dual stacked metal-insulator-metal capacitor and method for making same

#1. Field of the Invention

#The present invention generally relates to a dual stacked metal-insulator-metal (MIM) capacitor of a multilayer semiconductor device and a method of fabricating the same. More particularly, this invention relates to a dual stacked MIM capacitor, in which a bottom metal layer, including a metal plate of a first capacitor and a wiring level, and a top metal layer, including a metal plate of a second capacitor and a wiring level, are electrically connected to form a first terminal of the dual stacked MIM capacitor, while an intermediate metal layer forms a metal plate for both the first and the second capacitors and a second terminal of the dual stacked MIM capacitor.

#2. Description of the Related Art

#The foregoing and other aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

#FIG. 1 illustrates a schematic cross-section of a dual stacked MIM capacitor 100 in an exemplary embodiment of the present invention;

#FIG. 2A illustrates deposition of a stack in the fabrication of the dual stacked MIM capacitor 100 of FIG. 1 in an exemplary embodiment of the present invention;

#Generally, the present invention takes advantage of a bottom metal layer and a top metal layer, which are electrically connected together to form one terminal of a dual stacked MIM capacitor, and a single intermediate metal layer, which forms the other terminal of the dual stacked MIM capacitor. The dual stacked MIM capacitor of the present invention may provide the capacity density of two conventionally stacked MIM capacitors, with fewer metal layers.

#In various exemplary embodiments, deposition of a dielectric etchstop layer may occur after patterning the metal layers of the dual stacked MIM capacitor, and optionally, after a thin intervening interlayer dielectric may be deposited between the patterned metal layers and the dielectric etchstop layer.

#Referring to FIG. 1, a bottom metal layer 110, a portion of which forms a metal plate of a first MIM capacitor 140 of the dual stacked MIM capacitor 100 and another portion of which forms a wiring level, may be formed on a substrate 105. The another portion of the bottom metal layer 110, which forms a wiring level, may be electrically connected to another wiring level of another layer by a via.