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AssigneesRenesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.
InventorsChiemi Hashimoto, Yasuhiko Kawashima, Keizo Kawakita, Masahiro Moniwa, Hiroyasu Ishizuka, Akihiro Shimizu
Estimating the term…
Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode. Meanwhile, since the gate electrode in the peripheral circuit region has a gate length longer than that of the gate electrode in the memory array region, the thickness of the gate insulating film just below the center thereof is almost equal to that before the re-oxidation process.
A semiconductor integrated circuit device, in which a plurality of first MISFETs each having a first gate electrode are formed in a first region of a main surface of a semiconductor substrate and a plurality of second MISFETs each having a second gate electrode are formed in a second region of the main surface of the semiconductor substrate, the second gate electrode having a gate length longer than that of the first gate electrode,
A semiconductor integrated circuit device, in which a first MISFET having a first gate insulating film and a first gate electrode is formed in a first region of a main surface of a semiconductor substrate and a second MISFET having a second gate insulating film and a second gate electrode is formed in a second region of the main surface of the semiconductor substrate,
A semiconductor integrated circuit device, in which a first MISFET which constitutes a memory cell of a DRAM is formed in a first region of a main surface of a semiconductor substrate, a second MISFET which constitutes a part of a peripheral circuit of the DRAM is formed in a second region of the main surface of the semiconductor substrate, and a third MISFET which constitutes another part of the peripheral circuit of the DRAM is formed in a third region of the main surface of the semiconductor substrate,
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
Dependencies are inferred from the claim text.