Semiconductor device with reduced parasitic capacitance between impurity diffusion regions

A semiconductor device comprising:

• an underlying substrate having at least a surface layer made of semiconductor of a first conductivity type;
• a first layer formed on or over said underlying layer and made of semiconductor having a resistance higher than a resistance of the surface layer of said underlying substrate;
• a first impurity diffusion region formed in a partial surface region of said first layer and doped with impurities of a second conductivity type opposite to the first conductivity type, said first impurity diffusion region not reaching a surface of said underlying substrate;
• a second impurity diffusion region of the first conductivity type disposed in said first layer and spaced apart from said first impurity diffusion region by a certain distance in an in-plane direction, said second impurity diffusion region reaching the surface of said underlying substrate;
• and
• a first separation region disposed between said first and second impurity diffusion regions and comprising a trench formed in said first layer and dielectric material disposed at least in a partial internal region of the trench.