Thin film transistor array substrate and manufacturing method thereof
AssigneeLG. Philips LCD Co., Ltd.
InventorsWoong Kwon Kim, Heung Lyul Cho, Seung Hee Nam
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Abstract
A thin film transistor array substrate, and its manufacturing method, that is made using a three-round mask process. Gate patterns, each of which includes a gate line consisting of a transparent metal pattern and a gate metal pattern, a gate electrode, a lower gate pad, a lower data pad, and a pixel electrode are formed using a first mask process. A second mask process forms a gate insulating pattern and a semiconductor pattern. A third mask process forms source and drain patterns, each of which includes a data line, a source electrode, a drain electrode, an upper gate pad and an upper data pad. Additionally, the gate metal pattern on an upper portion of the pixel electrode is removed.
Claims29
A thin film transistor array substrate of a liquid crystal display, comprising:
- a gate line on a substrate;
- a gate insulating pattern over the gate line;
- a data line that crosses the gate line, wherein the gate insulating pattern is disposed between the gate line and the data line;
- a gate electrode on the substrate that is electrically connected to the gate line;
- a gate pad on the substrate, wherein the gate pad includes a lower gate pad and an upper gate pad, and wherein the gate pad is electrically connected to the gate line;
- a data pad on the substrate, wherein the data pad includes a lower data pad and an upper data pad;
- and wherein the data pad is electrically connected to the data line;
- a pixel electrode on the substrate and that is formed in a cell area defined by the gate line and the data line;
- a thin film transistor that includes the gate electrode, wherein the thin film transistor further includes a source electrode that is electrically connected to the data line, a drain electrode that is electrically connected to the pixel electrode, and a patterned semiconductor layer for providing a channel between the source electrode and the drain electrode;
- and
- a storage electrode that extends over part of the gate line and that electrically contacts the pixel electrode.
A thin film transistor array substrate of a liquid crystal display, comprising:
- a thin film transistor that includes a gate electrode on a substrate, wherein the thin film transistor further includes a source electrode, a drain electrode, and a patterned semiconductor layer for providing a channel between the source electrode and the drain electrode;
- a gate pad on the substrate that is electrically connected to the gate electrode, wherein the gate pad includes a lower gate pad on the substrate and an upper gate pad on the lower gate pad;
- and
- a pixel electrode on the substrate and that is electrically connected to the drain electrode.
A method of manufacturing a thin film transistor array substrate of a liquid crystal display, comprising the steps of:
- forming a first set of structures on a substrate using a first mask process, wherein the first set of structures includes a gate line, a gate electrode, a gate pad, a data pad, and a pixel electrode, wherein the first set of structures are comprised of a lower transparent conductive pattern and an upper metal pattern;
- forming a gate insulating layer, semiconductive layer, and ohmic contract layer over the first set of structures and over the substrate;
- forming a photo-resist pattern over the ohmic contact layer that is over the gate line and over the ohmic contact layer that is over the gate electrode;
- forming a second set of structures using a second mask process, wherein the second set of structures includes both a gate insulating pattern and a semiconductor pattern over the gate electrode, and a gate insulating pattern and a semiconductor pattern over the gate line, and wherein the second mask process exposes the pixel electrode, the data pad, and the gate pad;
- depositing a metal layer over the substrate, over the pixel electrode, over the data pad, over the gate pad, and over the second set of structures;
- and
- etching the deposited metal layer using a third mask process to form spaced apart source and drain electrodes, a gate pad contact hole, a data pad contact hole, data lines, and a storage electrode;
- wherein the drain electrode electrically contacts the pixel electrode, wherein the storage electrode electrically contacts the pixel electrode, and wherein the storage electrode is over at least part of the gate line
Dependencies are inferred from the claim text.