Thin film transistor array panel for a liquid crystal display

A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising steps of:

• forming a gate wire including a gate line and a gate electrode connected to the gate line, and a redundant data line;
• depositing a gate insulating layer, a semiconductor layer, and an ohmic contact layer;
• etching the gate insulating layer, the semiconductor layer, and the ohmic contact layer to form a semiconductor pattern, an ohmic contact layer pattern, and a gate insulating layer pattern having a first contact hole exposing the redundant data line;
• forming a data wire including a data line intersecting the gate line and connected to the redundant data pad through the first contact hole, a source electrode connected to the data line and neighboring the gate electrode, and a drain electrode separated from the source electrode and opposite to the source electrode with respect to the gate electrode;
• removing a portion of the ohmic contact layer pattern that is not covered by the data wire;
• depositing a passivation layer;
• etching the passivation layer to form a second contact hole exposing the drain electrode;
• and
• forming a pixel electrode connected to the drain electrode.

A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising steps of:

• forming a gate wire including a gate line and a gate electrode connected to the gate line and a redundant data line, wherein the gate wire and the redundant data line have a single-layered structure;
• depositing a gate insulating layer and a semiconductor layer;
• etching the gate insulating layer, and the semiconductor layer to form a semiconductor pattern of an island-like shape on the gate electrode, and a gate insulating layer pattern having a first contact hole exposing the redundant data line;
• forming a data wire including a data line connected to the redundant data line through the first contact hole, a source electrode, and a drain electrode;
• depositing and patterning the transparent conductive material to form a pixel electrode connected to the drain electrode in a pixel enclosed by the gate line and the data line;
• and
• depositing and patterning a passivation layer to form an opening exposing the pixel electrode.

A thin film transistor array panel for a liquid crystal display, comprising:

• an insulating transparent substrate;
• a gate wire including a gate line and a gate electrode connected to the gate line and having a single-layered structure on the insulating transparent substrate;
• a redundant data line formed by the same layer as the gate wire on the insulating transparent substrate;
• a gate insulating layer covering the gate wire and the redundant data line, and having a first contact hole exposing the redundant contact hole;
• a semiconductor layer formed on the gate insulating layer on the gate electrode;
• a data wire including a data line intersecting the gate line and connected to the redundant data pad through the first contact hole, a source electrode formed on a portion of the semiconductor layer and connected to the data line, and a drain electrode formed on a portion of the semiconductor layer and opposite to the source electrode with respect to the gate electrode;
• a pixel electrode connected to the drain electrode and formed on the gate insulating layer in a pixel enclosed by the gate line and the data line;
• and
• a passivation layer covering the pixel electrode and the data wire, and having an opening exposing the pixel electrode.