Methods and systems for integrated scheduling and resource management for a compiler
AssigneeIntel Corporation
InventorsChen Fu, Dong-Yuan Chen, Chengyong Wu, Dz-Ching Ju
Life of this patent
Estimating the term…
Abstract
A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.
Claims28
A computer implemented system for instruction scheduling and resource management comprising:
- a scheduling module configured to order a sequence of instructions;
- a function unit based finite state automata table configured to store a plurality of function unit vectors, each having as no more used bits than there are issue ports for a microprocessor, and one or more function unit template assignments for each function unit vector;
- and
- one or more microprocessor resource management components configured to match the sequence of instructions with at least one of the plurality of function unit vectors, and to arrange the sequence of instructions in accordance with at least one of the function unit template assignments corresponding to the at least one of the plurality of function unit vectors and in cooperation with the scheduling module.
A computer implemented method for integrated instruction scheduling and resource management for a compiler, comprising:
- scheduling a plurality of instructions into an issue cycle;
- classifying each of the plurality of instructions by function unit usage;
- matching the function unit usage for the plurality of instructions with a stored function unit vector;
- identifying one or more stored function unit template assignments, corresponding to the function unit vector, the function unit template assignments accounting for dispersal rules;
- and
- arranging the plurality of instructions in accordance with one of the identified function unit template assignments.
A computer readable medium having stored therein one or more sequences of instructions for causing one or more microprocessors to perform the acts for integrated instruction scheduling and resource management, the acts comprising:
- scheduling a plurality of instructions into an issue cycle;
- classifying each of the plurality of instructions by function unit usage;
- matching the function unit usage for the plurality of instructions with a stored function unit vector;
- identifying one or more stored function unit templates, corresponding to the function unit vector, the function unit template assignments accounting for the dispersal rules;
- and
- arranging the plurality of instructions in accordance with one of the identified function unit templates.
Dependencies are inferred from the claim text.