Method and system for logic-level circuit modeling
AssigneeCadence Design Systems, Inc.
InventorMark Steven Hahn
Life of this patent
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Abstract
A method for generating a model for a circuit having logic components is provided. The method includes identifying interface path logic components of the logic components so as to define shell logic, and identifying at least one of the logic components on which a constraint has been annotated so as to define constrained logic components. A subset of the logic components to preserve is then determined, the subset including the shell logic and the constrained logic components so as to define preserved logic. The model is then formed from the preserved logic. A highly accurate model can thus be created, while reducing computational and memory requirements. On-the-fly regeneration of the model is also possible, as is dominant path logic preservation.
Claims30
A method for generating a model for a circuit having logic components comprising the steps of:
- identifying interface path logic components of the logic components so as to define shell logic;
- identifying any logic components apart from the shell logic on which a constraint has been annotated so as to define constrained logic components;
- determining a subset of the logic components to preserve, the subset including the shell logic and the constrained logic components so as to define preserved logic;
- and
- forming the model from the preserved logic.
A method for generating a model for a circuit having logic components comprising the steps of:
- identifying interface path logic components of the logic components so as to define shell logic;
- identifying a slowest path and a fastest path between pairs of flip-flops of the logic components so as to define dominant paths, components in the dominant paths being defined as dominant path logic components;
- determining a subset of the logic components to preserve, the subset including the shell logic and the dominant path logic components;
- and
- constructing the model from the subset.
A system for modeling a circuit having logic components comprising:
- at least one model including a reduced set of the logic components, the reduced set of logic components including shell logic and constrained logic components, the constrained logic components including any logic components having annotated constraints.
Computer executable process steps operative to control a computer, stored on a computer-readable medium for facilitating generation of a timing model for a circuit having logic components, the process steps comprising:
- identifying the interface path logic components of the logic components so as to define shell logic;
- identifying any of the logic components apart from the shell logic on which a constraint has been annotated so as to define constrained logic components;
- determining a subset of the logic components to preserve, the subset including the shell logic and the constrained logic components so as to define preserved logic;
- and
- forming the model from the preserved logic.
Computer executable process steps operative to control a computer, stored on a computer-readable medium for facilitating generation of a timing model for a circuit having logic components, the process steps comprising:
- identifying interface path logic components of the logic components so as to define shell logic;
- identifying a slowest path and a fastest path between pairs of flip-flops of the logic components so as to define dominant paths, components in the dominant paths being defined as dominant path logic components;
- determining a subset of the logic components to preserve, the subset including the shell logic and the dominant path logic components;
- and
- constructing the model from the subset.
A method for repeatedly generating a model for a circuit having logic components comprising the steps of:
- a) identifying the interface path logic components of the logic components so as to define shell logic components;
- b) determining a subset of the logic components to preserve, the subset including the shell logic;
- c) forming the model from the subset of preserved logic components;
- d) using the model for a particular analysis;
- e) discarding the model;
- and
- f) repeating steps a) through c) at a later point in time to form a regenerated model.
Computer executable process steps operative to control a computer, stored on a computer-readable medium for facilitating multiple generation of a timing model for a circuit having logic components, the process steps comprising:
- a) identifying the interface path logic components of the logic components so as to define shell logic components;
- b) determining a subset of the logic components to preserve, the subset including the shell logic;
- c) forming the model from the subset of preserved logic components;
- d) using the model for a particular analysis;
- e) discarding the model;
- and
- f) repeating steps a) through c) at a later point in time to form a regenerated model.
Dependencies are inferred from the claim text.