Method and apparatus for fault injection using boundary scan for pins enabled as outputs
AssigneeLSI Logic Corporation
InventorThomas L. Langford II
Life of this patent
Estimating the term…
Abstract
Structure and associated methods of operation for an enhanced boundary scan register structure in an integrated circuit that permits flexible application of stuck-at faults or normal operation on each I/O pad of the IC. Each pad may be individually controlled to force a desired stuck-at fault or may be permitted to operate normally. The additional structure integrates with existing boundary scan register structures to minimize the need for additional logic and latches as compared to prior techniques and to minimize additional globally routed signals. Additional commands decoded by TAP command processing provides desired specialized control for the enhanced boundary scan register.
Claims12
In an integrated circuit design, an improved boundary scan cell, the improvement comprising:
- an enhanced boundary scan enable signal to controllably enable enhanced operation of said boundary scan cell;
- an AND gate having an output and having a first input coupled to the output of a capture flip-flop of said boundary scan cell and having a second input coupled to the enhanced boundary scan enable signal;
- and
- an OR gate having a first input coupled to a boundary scan mode signal of said boundary scan cell and having a second input coupled to the output of said AND gate and having an output coupled to the selection input of a multiplexer of said boundary scan cell for selectively applying the output of a hold latch of said boundary scan cell to an outbound operational signal of said boundary scan cell.
A boundary scan cell comprising:
- a first signal pathway selectively configured to apply an inbound operational signal to an outbound operational signal path;
- and
- a second signal path for selectively applying a predetermined fault signal to said outbound operational signal path.
In an integrated circuit configured for boundary scan capability, a method for injecting a fault condition on an I/O signal pad of said integrated circuit comprising the steps of:
- loading a fault signal representing said fault condition into the hold latch of the boundary scan register associated with said I/O signal pad;
- loading the capture flip-flop of said boundary scan register with a cell enable signal value;
- applying a global enable signal to an enhanced operation enable input of said boundary scan register;
- and
- applying said fault signal to said I/O signal pad in response to the combination of the application of said global enable signal to said enhanced operation enable input and the loading of said cell enable signal in said capture flip-flop.
In an integrated circuit design, an improved boundary scan cell having an inbound operational signal and having an outbound operational signal and having a scan input signal and having a capture flip-flop with an input selectively coupled either to said inbound operational signal or to said scan input signal and having a hold latch with an input coupled to the output of said capture flip-flop and with an output selectively applied through a multiplexer to said outbound operational signal wherein said multiplexer has a selection input coupled to a boundary scan mode signal, the improvement comprising:
- an enhanced boundary scan enable signal to enable enhanced operation of the improved boundary scan register;
- an AND gate having an output and having a first input coupled to the output of the capture flip-flop and having a second input coupled to the enhanced boundary scan enable signal;
- and
- an OR gate having a first input coupled to the boundary scan mode signal and having a second input coupled to the output of said AND gate and having an output coupled to the selection input of said multiplexer.
Dependencies are inferred from the claim text.