US 2003/0196163 A1Published application

ACS circuit and viterbi decoder with the circuit

AssigneeMediatek Inc.

InventorsHong-Ching Chen, Wen-Zen Shen, Der-Tsuey Shen Wang

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Abstract

An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Claims10

Dependent claims

An ACS (Add-Compare-Select) circuit, which is used in a Viterbi decoder with respect to a trellis, for receiving a plurality of previous candidate state metrics respective to a trellis state in the trellis and a first branch metric respective to a first branch from the trellis state, outputting a first output candidate state metric respective to the first branch, the ACS circuit comprising:

a plurality of registers for storing the plurality of previous candidate state metrics respective to the trellis state;
and
an ACS processor for receiving the values stored in the registers and the first branch metric, outputting the first output candidate state metric;
wherein the ACS processor comprising:
a plurality of adders for adding each of the value stored in the registers and the first branch metric to generate a plurality of addition results;
a comparator for comparing the values stored in the registers, and outputting a comparison signal indicating which one is minimum;
and
a plurality of selectors for selecting the first output candidate state metric from the addition results according to the comparison signal.

5 more elements

two registers for storing the previous candidate state metrics respective to the trellis state;
and
an ACS processor for receiving the values stored in the registers and the first branch metric, outputting the first output candidate state metric;
wherein the ACS processor comprising:
a first adder for adding the value stored in a first register and the first branch metric to generate a first addition result;
a second adder for adding the value stored in a second register and the first branch metric to generate a second addition result;
a comparator for comparing the value stored in the first register and the value stored in the second register, and outputting a comparison signal indicating which one is minimum;
and
a first selector for selecting either the first addition result or the second addition result as the first output candidate state metric according to the comparison signal.

6 more elements

Dependencies are inferred from the claim text.