Systolic architecture for comma-free reed-solomon decoding circuit

Abstract

A Comma-Free Reed-Solomon decoding circuit based on systolic array architecture that applies to a cell search in a wideband code division multiple access system, and more particularly a decoding circuit that employs a systolic array in its circuit structure. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a correlating comparison, and outputs the results of the correlating comparison to the boundary processing element, so as to acquire the decoding results required by the Comma-Free Reed-Solomon code. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.

Dependencies are inferred from the claim text.