Method of testing a circuit using an output vector

A test mode regulation device for a decode circuit coupled to a plurality of address input pathways, a reset signal pathway, and a plurality of test vector output pathways, and further configured to receive a latch enable pathway and perform at least one decode circuit operation, comprising:

• an additional test vector output pathway configured to couple to said decode circuit and further configured to transmit a disable signal in response to a final decode circuit operation;
• and
• a logic unit configured to electrically interpose between said latch enable pathway and said decode circuit, wherein said logic unit comprises:
• a first input coupled to said latch enable pathway,
• a second input coupled to said additional test vector output pathway, and
• an output coupled to said decode circuit,
• and said logic unit configured to prevent a drive communication between said latch enable pathway and said decode circuit in response to said disable signal.

A test device, comprising:

• a test vector decode circuit;
• an output node coupled to said decode circuit;
• and
• a lockout device coupled to said decode circuit and configured to decouple said decode circuit from said output node after an operation of said decode circuit.

A test vector decode circuit comprising:

• a logic circuit;
• at least one input terminal coupled to said logic circuit;
• a latch terminal coupled to said logic circuit;
• at least one output terminal coupled to said logic circuit;
• and
• a latch disabling device coupled to said output terminal and to said latch terminal, said latch disabling device configured to activate in response to an output vector from said output terminal, and
• said output terminal configured to transmit said output vector in response to a combination of:
• an input signal received at said input terminal, and
• a logic circuit operation.

A test circuit comprising:

• a test vector decode device;
• an input node coupled to said test vector decode device;
• an output node coupled to said test vector decode device;
• a latch node;
• and
• a latch device coupled to said latch node and configured to receive a latch prompt signal and further configured to alternatively receive an initial signal and an anti-latch signal, said latch device further configured to allow electrical communication between said input node and said output node in response to a combination of said initial signal and said latch prompt signal and to prevent said electrical communication in response to said anti-latch signal.

A lockout device for a decode circuit having at least one decode function, including a test-mode-completion decode function comprising:

• a latch control terminal configured to couple to said decode circuit and further configured to alternatively transmit:
• a lockout signal in response to said test-mode-completion decode function of said decode circuit, and
• an admission signal;
• and
• a logic circuit, further comprising:
• an output terminal configured to couple to said decode circuit,
• a first input terminal configured to receive a decode initiation signal, said logic circuit configured to initiate said decode function responsive to said decode initiation signal, and
• a second input terminal coupled to said latch control terminal and further configured to prevent said decode function responsive to said lockout signal.

A latch regulator for a circuit, comprising:

• a lockout pathway configured to carry a disable signal having a first value and a second value;
• and
• a logic apparatus having:
• a first input node coupled to said lockout pathway,
• a second input node configured to receive a latch prompt signal, and
• an output node configured to couple to said circuit,
• and said logic apparatus configured to recognize a change in said latch prompt signal while said disable signal has said first value and further configured to disregard said change in said latch prompt signal while said disable signal has said second value.

A method for regulating the ability of a testing circuit to latch at least one output vector, comprising:

• designating one output vector as a lockout vector;
• allowing at least one latching;
• associating at least one latching with a first change of said lockout vector;
• initiating said first change of said lockout vector;
• allowing further latching only in response to a second change of said lockout vector;
• and
• allowing said second change in lockout vector only in response to further latching and to resetting said lockout vector.

A method of testing a circuit, comprising:

• receiving at least one address input;
• receiving at least one latching signal;
• performing a decoding operation on each address input;
• transmitting a result of said decoding operation as at least one output test vector in response to each latching signal;
• driving said circuit with each output test vector;
• generating a latch prevention signal;
• and
• overriding any subsequent latching signal with said latch prevention signal.

A method for testing an external circuit, comprising:

• subjecting an address input to a logic function;
• generating an output vector;
• driving said external circuit with said output vector;
• generating a lockout signal;
• and
• prohibiting subjecting an address input to a logic function during a generation of said lockout signal.

A method of regulating the value of a test signal, comprising:

• initiating a latch mode;
• accepting an input signal;
• performing a logic operation on said input signal;
• deriving an output signal;
• and
• initiating an input lockout mode.

A method of protecting a test circuit from receiving a subsequent latching signal after receiving at least one prior latching signal, comprising:

• allowing at least one prior latching signal to reach said test circuit;
• performing a test circuit operation for each prior latching signal;
• providing a lockout signal;
• and
• stopping any subsequent latching signal with said lockout signal.