Systems and methods for testing processors
AssigneeIntel Corporation
InventorsKiran A. Padwekar, Jesse Pan, Sudhakar Bhat
Life of this patent
Estimating the term…
Abstract
Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.
Claims29
A system comprising:
- a memory hierarchy to hold original code;
- a storage unit coupled to the memory hierarchy;
- a processor
- to execute the original code from the memory hierarchy,
- after entering a probe break, to transfer the original code from the memory hierarchy to the storage unit and to transfer load test code to the memory hierarchy, and to execute the test code from the memory hierarchy, and
- after executing the test code, to reload the original code from the storage unit to the memory hierarchy and to resume executing the original code from the memory hierarchy.
A method for testing a processor, comprising:
- executing original code from a memory hierarchy;
- upon entering a probe break,
- transferring the original code from the memory hierarchy to a storage device, saving information representing a current state of the processor, loading a probe mode handler into the memory hierarchy;
- during the probe break,
- executing the probe mode handler from the memory hierarchy, to test the processor;
- accessing the current state information by the probe mode handler;
- after the probe break,
- loading the original code from the storage device to the memory hierarchy, resuming execution of the original code from the memory hierarchy.
A method for testing a processor, comprising:
- entering a probe break,
- saving information representing a current state of the processor,
- loading a probe mode handler into a memory hierarchy;
- executing the probe mode handler;
- while executing the probe mode handler during the probe break, accessing the saved current state information.
Dependencies are inferred from the claim text.