Processor condition sensing circuits, systems and methods

An electronic system comprising:

• a data processing device including a semiconductor chip and an electronic processor on-chip;
• and
• a host computer external to said chip and connected to said data processing device, said host computer having a speed of operation which is slower than said electronic processor, said data processing device further comprising an on-chip condition sensor coupled to said host computer and connected to stop said electronic processor automatically upon occurrence of a predetermined condition of operation of said data processing device.

A method of controlling, by a host computer, operations of an electronic processor fabricated on a semiconductor chip and having a speed exceeding the speed of the host computer and seemingly incompatible with control by the host computer, the method comprising the steps of:

• loading an on-chip condition sensor from the host computer with information at a lower speed of the host computer to establish the function desired of the on-chip condition sensor;
• and,
• sensing the operations of the electronic processor with the on-chip condition sensor, wherein the on-chip condition sensor performs the established function at a speed compatible with the speed of the electronic processor.

A data processing device comprising:

• a program counter;
• and
• program counter trace stack means for holding a predetermined number of addresses defining a history of address discontinuities in operation of said program counter.

A method of monitoring operations of a data processing device having an electronic processor fabricated on a semiconductor chip, the method comprising the steps of:

• sensing the operations of the electronic processor with a program counter trace stack on-chip that has a speed of operation compatible with the speed of the electronic processor;
• and
• transferring the contents of the program counter trace stack by serial scan-out to a host computer at a slower rate compatible with the speed of the host computer for monitoring purposes.

A data processing device comprising:

• a program counter, a program counter stack, a trace stack and means for causing the program counter to count through a series of addresses;
• and
• a control circuit for entering a jump address into said program counter in substitution for a current address in the series, thereby establishing a discontinuity, said control circuit including means for pushing the current address onto the program counter stack and the jump address onto the trace stack.

An electronic system comprising:

• a data processing device including a semiconductor chip and an electronic processor on-chip;
• and
• a host computer off-chip and coupled to said data processing device, said host computer having a speed of operation which is slower than said electronic processor, said data processing device further comprising an on-chip trace stack, and a stack-full signaling circuit having an input connected to said trace stack.

A method of tracing operations of a data processing device having a program counter and program counter stack and a circuit for making the counter count through a continuous series of addresses and a circuit for entering a jump address into the program counter in substitution for a current address in the series, the method comprising the steps of

• pushing the latest address onto the program counter stack and pushing the new address onto a separate trace stack.