Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories
AssigneeLSI Logic Corporation
InventorsMukesh K. Puri, Ghasi R. Agrawal
Life of this patent
Estimating the term…
Abstract
An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.
Claims20
An apparatus comprising:
- a controller circuit configured to present one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation;
- and
- a BISR assembly circuit comprising one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution, wherein said memory blocks are remapped in response to said count values during one or more of said BISR operations.
An apparatus for remapping a memory circuit comprising:
- means for presenting one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation of said memory circuit;
- means for generating one or more clock cycle count values in response to a repair solution;
- and
- means for controlling said one or more BISR operations in response to said count values.
A method for remapping a memory circuit comprising the steps of:
- (A) presenting one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation of said memory circuit;
- (B) generating one or more clock cycle count values in response to a repair solution;
- and
- (C) controlling said one or more BISR operations in response to said count values.
Dependencies are inferred from the claim text.