Transparent software emulation as an alternative to hardware bus lock
AssigneeHewlett-Packard Development Company, L.P.
InventorRobert J. Brooks
Life of this patent
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Abstract
A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.
Claims20
An apparatus, implemented in a computer system, for emulating a hardware bus lock, the computer system comprising a central processing unit (CPU) executing an operating system (O/S), processors, and a main memory, the apparatus, comprising:
- a fault handler module operating on the CPU, the fault handler module including an emulation module;
- the main memory accessible by the CPU and the processors, the main memory comprising a reserved memory block and a page table;
- a bus lock semaphore stored in the reserved memory block, wherein the bus lock semaphore is invisible to the O/S;
- and
- a page table semaphore stored in the reserved memory block, wherein exclusive access to native page tables is maintained, and wherein page tables cross reference virtual addresses and physical addresses.
A software emulation mechanism operating in a computer system having a main memory comprising page tables to translate between physical and virtual addresses, and translation lookaside buffers (TLBs), the software emulation mechanism preventing hardware bus lock, comprising:
- a configuration register comprising a lock fault enable bit;
- a lock semantic indication supplied by an execution unit;
- a logic device that receives the lock fault enable bit and the lock semantic and outputs a lock fault to an exception unit;
- a bus lock semaphore accessible by the emulation mechanism;
- a page table semaphore that controls access to the page tables;
- a fault handler that acquires the bus lock and page table semaphore to prevent access to the page tables, the fault handler using the software emulation mechanism to invalidate page table entries and to purge page table entries in TLBs corresponding to the invalidated page table entries, wherein the exception unit is prevented from executing a hardware bus lock.
A method, executed in a computer system including processors, translation lookaside buffers, translation lookaside buffers (TLBs) for translating between virtual addresses and physical addresses, and a memory, the memory including page tables, for preventing a hardware bus lock by software emulation, comprising:
- at a device in the computer system, attempting an operation capable of causing the hardware bus lock, wherein the operation comprises accessing a desired location in the computer system;
- at a fault handler, receiving an indication of the attempted operation and acquiring a bus lock semaphore;
- providing the bus lock semaphore to the device;
- caching the bus lock semaphore at a cache associated with the device;
- at the fault handler:
- acquiring a page table protection mechanism,
- invalidating selected page table entries, wherein access to the desired location is prevented, and
- purging any TLB page tables associated with the desired location;
- and
- executing an instruction sequence to cause a fault-on-bus-lock.
A method for software emulation of hardware bus lock in a computer system, comprising:
- attempting a bus lock operation;
- acquiring a bus lock semaphore;
- providing the bus lock semaphore to a device attempting the bus lock operation;
- acquiring a page table semaphore;
- invalidating page table entries to prevent access to a location in the computer system referenced by the bus lock operation;
- purging translation lookaside buffer pages associated with the location;
- inserting local translation entries;
- and
- executing a clone instruction without lock semantics.
Dependencies are inferred from the claim text.