Cached-counter arrangement in which off-chip counters are updated from on-chip counters
AssigneeInternational Business Machines Corporation
InventorKerry Christopher Imming
Life of this patent
Estimating the term…
Abstract
In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter in main memory is updated using the cache memory counter value. This arrangement economizes on the use of main memory access bandwidth.
Claims29
A method of maintaining a counter in a processing device, comprising:
- maintaining a first counter in a memory that is on board a processing integrated circuit;
- fetching a counter value from a second counter stored in a memory device that is separate from the processing integrated circuit;
- adding a counter value from the first counter to the fetched counter value from the second counter to produce a sum counter value;
- and
- writing the sum counter value into the second counter.
A method of maintaining a counter in a processing device, comprising:
- maintaining a first counter on board a processing integrated circuit;
- maintaining a second counter in a memory that is separate from the processing integrated circuit;
- detecting a trigger event;
- and
- in response to the trigger event, updating the second counter based on a counter value of the first counter.
A method of resetting a counter, comprising:
- maintaining a first counter;
- maintaining a second counter;
- clearing the first counter;
- setting a reset-pending bit;
- detecting a trigger event;
- and
- in response to the trigger event and the reset-pending bit, loading into the second counter a counter value of the first counter.
A method of maintaining counters in a processing device, comprising:
- maintaining a plurality of first counters in a memory that is on board a processing integrated circuit;
- maintaining a like plurality of second counters in a memory device that is separate from the processing integrated circuit, each of the second counters being associated with a respective one of the first counters;
- detecting a trigger event with respect to a particular one of the first counters;
- and
- in response to the trigger event, updating all of the second counters based on counter values of the first counters respectively associated with the second counters.
A processing device, comprising:
- a processing integrated circuit including an onboard memory;
- and
- a memory device that is separate from, and operatively coupled to, the processing integrated circuit;
- wherein the processing integrated circuit is programmed to:
- maintain a first counter in the on-board memory;
- fetch a counter value from a second counter stored in the memory device;
- add a counter value from the first counter to the fetched counter value from the second counter to produce a sum counter value;
- and
- write the sum counter value into the second counter.
A processing device, comprising:
- a processing integrated circuit including an onboard memory;
- and
- a memory device that is separate from, and operatively coupled to, the processing integrated circuit;
- wherein the processing integrated circuit is programmed to:
- maintain a first counter in the on-board memory;
- maintain a second counter in the memory device;
- detect a trigger event;
- and
- in response to the trigger event, update the second counter based on a counter value of the first counter.
A processing device, comprising:
- a processing integrated circuit including an onboard memory;
- and
- a memory device that is separate from, and operatively coupled to, the processing integrated circuit;
- wherein the processing integrated circuit is programmed to:
- maintain a first counter in the on-board memory;
- maintain a second counter in the memory device;
- clear the first counter;
- set a reset-pending bit;
- detect a trigger event;
- and
- in response to the trigger event and the reset-pending bit, load into the second counter a counter value of the first counter.
A processing device, comprising:
- a processing integrated circuit including an onboard memory;
- and
- a memory device that is separate from, and operatively coupled to, the processing integrated circuit;
- wherein the processing integrated circuit is programmed to:
- maintain a plurality of first counters in the on-board memory;
- maintain a like plurality of second counters in the memory device, each of the second counters being associated with a respective one of the first counters;
- detect a trigger event with respect to a particular one of the first counters;
- and
- in response to the trigger event, update all of the second counters based on counter values of the first counters respectively associated with the second counters.
A computer program product for use with a processing device that includes a processing integrated circuit and a memory device operatively coupled to the processing integrated circuit, the processing integrated circuit having an on-board memory, the computer program product comprising:
- a medium readable by a computer, the computer readable medium having computer program code adapted to:
- maintain a first counter in the on-board memory;
- fetch a counter value from a second counter stored in the memory device;
- add a counter value from the first counter to the fetched counter value from the second counter to produce a sum counter value;
- and
- write the sum counter value into the second counter.
A computer program product for use with a processing device that includes a processing integrated circuit and a memory device operatively coupled to the processing integrated circuit, the processing integrated circuit having an on-board memory, the computer program product comprising:
- a medium readable by a computer, the computer readable medium having computer program code adapted to:
- maintain a first counter in the on-board memory;
- maintain a second counter in the memory device;
- detect a trigger event;
- and
- in response to the trigger event, update the second counter based on a counter value of the first counter.
A computer program product for use with a processing device that includes a processing integrated circuit and a memory device operatively coupled to the processing integrated circuit, the processing integrated circuit having an on-board memory, the computer program product comprising:
- a medium readable by a computer, the computer readable medium having computer program code adapted to:
- maintain a first counter in the on-board memory;
- maintain a second counter in the memory device;
- clear the first counter;
- set a reset-pending bit;
- detect a trigger event;
- and
- in response to the trigger event and the reset-pending bit, load into the second counter a counter value of the first counter.
A computer program product for use with a processing device that includes a processing integrated circuit and a memory device operatively coupled to the processing integrated circuit, the processing integrated circuit having an on-board memory, the computer program product comprising:
- a medium readable by a computer, the computer readable medium having computer program code adapted to:
- maintain a plurality of first counters in the on-board memory;
- maintain a like plurality of second counters in the memory device, each of the second counters being associated with a respective one of the first counters;
- detect a trigger event with respect to a particular one of the first counters;
- and
- in response to the trigger event, update all of the second counters based on counter values of the first counters respectively associated with the second counters.
Dependencies are inferred from the claim text.