Apparatus and method for extending address modes in a microprocessor

An instruction set extension apparatus, for providing extended address mode capabilities to an existing instruction set, the instruction set extension apparatus comprising:

• an escape tag, for reception by translation logic, and for indicating that accompanying parts of a corresponding instruction prescribe an extended operation to be performed by a microprocessor, wherein said escape tag is a first opcode within the existing instruction set;
• an extended address mode specifier, coupled to said escape tag and being one of said accompanying parts, for prescribing one of a plurality of address modes that corresponds to said extended operation;
• and
• extended execution logic, coupled to said translation logic, for executing said extended operation using said one of said plurality of address modes, wherein the existing instruction set provides only for existing address modes other than said one of said plurality of address modes.

A method for extending an existing instruction set architecture to provide for programmable specification of an extended address mode within a microprocessor, the method comprising:

• providing an extended instruction, the extended instruction including an extended tag along with an extended prefix, wherein the extended tag is a first opcode entity according to the existing instruction set architecture;
• prescribing, via the extended prefix and remaining parts of the extended instruction, the extended address mode and a specified operation, wherein the existing instruction set architecture exclusively provides instructions for specifying address modes other than the extended address mode;
• and
• executing the specified operation according to the extended address mode.