US 2003/0196075 A1 · Memory disambiguation for large instruction windows

Abstract

A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction window of a processor. Some store queue entries include resolved store addresses, and some do not. The store forwarding buffer is a set-associative buffer that has entries allocated for store instructions as store addresses are resolved. Each entry in the store forwarding buffer is allocated into a set determined in part by a subset of the store address. When the set in the store forwarding buffer is full, an older entry in the set is discarded in favor of the newly allocated entry. A version count buffer including an array of overflow indicators is maintained to track overflow occurrences. As load addresses are resolved for load instructions in the instruction window, the set-associative store forwarding buffer can be searched to provide memory disambiguation.

Claims30

Dependent claims

A system comprising:

an instruction window to hold instructions including a first plurality of store instructions;
a first queue to hold the first plurality of store instructions;
and
a set-associative buffer to hold a second plurality of store instructions organized in a plurality of sets to be searched for store instructions upon which any of a plurality of load instructions depend, each of the plurality of sets including a subset of the first plurality of store instructions, at least one of the second plurality of store instructions having resolved memory addresses included therewith.

1 more element

Dependencies are inferred from the claim text.

Memory disambiguation for large instruction windows

Life of this patent

Memory disambiguation for large instruction windows

Life of this patent

Abstract

Claims30